Lead Static Timing Analysis Engineer

1 day ago


Bengaluru, Karnataka, India Fiori Technology Solutions Inc Full time ₹ 12,00,000 - ₹ 36,00,000 per year

We are seeking an experienced Lead STA Engineer to take ownership of the static timing closure process for complex ASIC/SoC designs. In this role, you will lead timing sign-off activities, coordinate with cross-functional teams, and ensure designs meet performance, power, and area targets while achieving first-pass silicon success.

Key Responsibilities:

  • Own and drive timing closure for multiple blocks or full-chip designs from synthesis through tape-out.
  • Develop and maintain timing constraints (SDC) for synthesis, place-and-route, and sign-off flows.
  • Perform setup, hold, recovery, and removal analysis using industry-standard STA tools.
  • Analyze timing reports and debug violations, providing guidance to physical design, RTL, and DFT teams.
  • Work closely with clock, power, and signal integrity engineers to address timing and noise-related issues.
  • Lead STA reviews with design and physical implementation teams, ensuring issues are tracked and resolved.
  • Collaborate with methodology teams to enhance STA flows and timing sign-off quality.
  • Contribute to methodology improvements for STA and PNR flows.
  • Mentor and guide junior engineers in STA and timing-driven PNR techniques.
Requirements

Must-Have:

  • Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering or related field.
  • 10-12 years of hands-on experience in STA for large, complex ASIC/SoC designs.
  • Proven PNR experienceto handle flat SoC designs in Cadence flow. Solid understanding of multi-mode, multi-corner (MMMC) timing analysis.
  • Proficiency in timing constraints writing (SDC), clock domain crossing (CDC) considerations, and asynchronous interface analysis.
  • Experience with ECO timing closure and post-route sign-off.
  • Prior experience in team leadership or technical mentoring.

Nice-to-Have:

  • Familiarity with scripting languages (Tcl, Perl, Python) for flow automation.
  • Exposure to low-power design techniques (UPF/CPF).
  • Knowledge of signal integrity, EM/IR drop impacts on timing.
  • Experience in the automotive industry is a plus


  • Bengaluru, Karnataka, India Eduplex services private limited Full time ₹ 20,00,000 - ₹ 30,00,000 per year

    Static Timing Analysis (STA) LeadLocation: Bangalore, KAExperience: 7–18 YearsBudget: Up to 30 LPA (DoE)Industry: Semiconductors | ASIC | SoC | AI/Networking ChipsJob Type: Full-TimeJob OverviewWe are seeking a highly skilled Static Timing Analysis (STA) Lead to drive timing closure for large-scale, high-performance ASIC/SoC designs. The ideal candidate...


  • Bengaluru, Karnataka, India LeadSoc Technologies Pvt Ltd Full time ₹ 15,00,000 - ₹ 25,00,000 per year

    Static Timing Analysis (STA) Engineer Job DescriptionJob SummaryThe Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with...


  • Bengaluru, Karnataka, India Fiori Technology Solutions Inc Full time ₹ 20,00,000 - ₹ 25,00,000 per year

    We are seeking an experienced Lead STA Engineer to take ownership of the static timing closure process for complex ASIC/SoC designs. In this role, you will lead timing sign-off activities, coordinate with cross-functional teams, and ensure designs meet performance, power, and area targets while achieving first-pass silicon success.Key Responsibilities:Own...


  • Bengaluru, Karnataka, India Careernet Full time ₹ 15,00,000 - ₹ 25,00,000 per year

    Key Skills: Static Timing Analysis,PrimeTimeRoles and Responsibilities:Conduct block-level and full-chip static timing analysis across all phases of development.Develop timing methodologies and infrastructure from RTL synthesis to timing closure.Collaborate with architects and designers to define block and chip-level timing constraints.Define analysis...


  • Bengaluru, Karnataka, India beBeeStressEngineer Full time ₹ 17,00,000 - ₹ 25,00,000

    Static Analysis EngineerAre you a skilled static analysis engineer with expertise in stress engineering? We are seeking a talented individual to join our team as a Static Analysis Engineer. In this role, you will be responsible for creating and modifying finite element models (FEM) for primary and secondary structures using GFEM/DFEM.Key...


  • Bengaluru, Karnataka, India Capgemini Engineering Full time

    Experience: 5+yearsLocation: BangaloreJob Description:As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and process...


  • Bengaluru, Karnataka, India Capgemini Engineering Full time

    Experience: 5+years Location: Bangalore Job Description: As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and process...


  • Bengaluru, Karnataka, India Capgemini Engineering Full time

    Job DescriptionExperience: 5+yearsLocation: BangaloreJob Description:As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and...


  • Bengaluru, Karnataka, India Capgemini Engineering Full time

    Experience: 5+yearsLocation: BangaloreJob Description:As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and process...


  • Bengaluru, Karnataka, India Capgemini Engineering Full time ₹ 20,00,000 - ₹ 25,00,000 per year

    Experience: 5+yearsLocation: BangaloreJob Description:As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and process...