STA(Static Timing Analysis) Engineer

7 days ago

Bengaluru, Karnataka, India Capgemini Engineering Full time ₹ 20,00,000 - ₹ 25,00,000 per year

Experience
: 5+years

Location
: Bangalore

Job Description:

As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and process corners.

Key Responsibilities:

  • Own full-chip and block-level timing closure across RTL, synthesis, and physical implementation stages.
  • Develop and validate timing constraints (SDC) for blocks, partitions, and full-chip designs.
  • Perform timing analysis using industry-standard tools (e.g., PrimeTime, Tempus).
  • Collaborate with design and architecture teams to define timing requirements and resolve timing violations.
  • Analyze timing scenarios, margins, and corner cases.
  • Integrate third-party IPs and derive timing signoff requirements.
  • Optimize timing paths and reduce signoff corners by merging modes.
  • Automate STA flows using scripting languages.
  • Support test mode timing closure (e.g., scan shift, scan capture, BIST).

Primary Skills:

  • Static Timing Analysis (STA):
    Deep expertise in STA tools like Synopsys PrimeTime, Cadence Tempus.
  • Timing Constraints Development:
    Proficient in writing and validating SDC constraints.
  • Scripting Languages:
    Strong skills in TCL, Perl, Python for automation.
  • ASIC/SoC Design Knowledge:
    Understanding of synthesis, physical design, and backend flows.
  • Corner and Mode Analysis:
    Experience with timing corners, process variations, and signal integrity.
  • Constraint Debugging:
    Familiarity with tools like Synopsys GCA (Galaxy Constraint Analyzer).

Secondary Skills:

  • Tool Proficiency:
    Experience with tools like Genus, Timevision, Fishtail, Tweaker.
  • Low-Power Design:
    Knowledge of UPF, multi-voltage domains, and power gating.
  • Custom IP Integration:
    Handling of PLLs, SerDes, ADC/DAC, GPIO, HSIO.
  • Communication & Collaboration:
    Strong interpersonal skills for cross-functional teamwork.
  • Mentorship:
    Ability to guide and mentor junior engineers.
  • Process Node Experience:
    Familiarity with advanced nodes (3nm, 5nm, 7nm, FinFET).

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