Static Timing Analysis
16 hours ago
Static Timing Analysis (STA) EngineerJob Summary The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with design and physical design teams to achieve the target operating frequency and performance metrics. Key ResponsibilitiesTiming Sign-off and AnalysisTiming Closure Ownership: Drive all aspects of timing closure from pre-layout to post-layout for blocks, sub-systems, and/or the full chip.Constraint Management: Develop, validate, and maintain Synopsys Design Constraints (SDC) and timing constraints for all functional and test modes (e.g., Scan, MBIST).MMMC Analysis: Perform comprehensive timing analysis across multiple operating corners (Process, Voltage, Temperature - PVT) and various modes (Multi-Mode Multi-Corner).Critical Path Identification: Analyze timing reports to identify and debug critical paths and resolve all Setup and Hold violations.Signal Integrity (SI) & Noise: Incorporate advanced timing effects such as on-chip variation (OCV), signal integrity (crosstalk), and voltage drop (IR-drop aware STA) into the sign-off process.Methodology and FlowDevelop, maintain, and enhance STA flows and methodologies to improve efficiency, robustness, and reduce analysis runtime.Automate repetitive tasks and report generation using scripting languages.Generate final timing reports and sign-off collateral for tape-out.EducationBachelor's or Master's degree in Electrical Engineering (EE), Electronics Engineering, VLSI, or a related field.Technical Skills & ExperienceExperience: 3+ years of experience in STA.EDA Tools: Expert proficiency with industry-standard Electronic Design Automation (EDA) tools from vendors like Synopsys (e.g., Fusion Compiler, ICC2, Primetime), Cadence (e.g., Innovus), or Mentor Graphics.Soft SkillsExcellent analytical, debugging, and problem-solving skills.Strong verbal and written communication skills.Ability to work effectively in a team environment and collaborate across different engineering disciplines.
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Static Timing Analysis
16 hours ago
Bengaluru, Karnataka, India, Karnataka LeadSoc Technologies Pvt Ltd Full timeStatic Timing Analysis (STA) Engineer Job DescriptionJob SummaryThe Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with...
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Static Timing Analysis
2 weeks ago
Bengaluru, Karnataka, India LeadSoc Technologies Pvt Ltd Full time ₹ 15,00,000 - ₹ 25,00,000 per yearStatic Timing Analysis (STA) Engineer Job DescriptionJob SummaryThe Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with...
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Static Timing Analysis
1 week ago
Bengaluru, Karnataka, India Eduplex services private limited Full time ₹ 20,00,000 - ₹ 30,00,000 per yearStatic Timing Analysis (STA) LeadLocation: Bangalore, KAExperience: 7–18 YearsBudget: Up to 30 LPA (DoE)Industry: Semiconductors | ASIC | SoC | AI/Networking ChipsJob Type: Full-TimeJob OverviewWe are seeking a highly skilled Static Timing Analysis (STA) Lead to drive timing closure for large-scale, high-performance ASIC/SoC designs. The ideal candidate...
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STA(Static Timing Analysis) Engineer
16 hours ago
Bengaluru, Karnataka, India, Karnataka Capgemini Engineering Full timeExperience: 5+yearsLocation: BangaloreJob Description:As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and process...
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SOC Static Timing Analysis Engineer
1 week ago
Bengaluru, Karnataka, India Careernet Full time ₹ 15,00,000 - ₹ 25,00,000 per yearKey Skills: Static Timing Analysis,PrimeTimeRoles and Responsibilities:Conduct block-level and full-chip static timing analysis across all phases of development.Develop timing methodologies and infrastructure from RTL synthesis to timing closure.Collaborate with architects and designers to define block and chip-level timing constraints.Define analysis...
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STA(Static Timing Analysis) Engineer
3 weeks ago
Bengaluru, Karnataka, India Capgemini Engineering Full timeJob DescriptionExperience: 5+yearsLocation: BangaloreJob Description:As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and...
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STA(Static Timing Analysis) Engineer
4 weeks ago
Bengaluru, Karnataka, India Capgemini Engineering Full timeExperience: 5+yearsLocation: BangaloreJob Description:As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and process...
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Lead Static Timing Analysis Engineer
1 week ago
Bengaluru, Karnataka, India Fiori Technology Solutions Inc Full time ₹ 12,00,000 - ₹ 36,00,000 per yearWe are seeking an experienced Lead STA Engineer to take ownership of the static timing closure process for complex ASIC/SoC designs. In this role, you will lead timing sign-off activities, coordinate with cross-functional teams, and ensure designs meet performance, power, and area targets while achieving first-pass silicon success.Key Responsibilities:Own...
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STA(Static Timing Analysis) Engineer
1 week ago
Bengaluru, Karnataka, India Capgemini Engineering Full time ₹ 20,00,000 - ₹ 25,00,000 per yearExperience: 5+yearsLocation: BangaloreJob Description:As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and process...
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Static Time Analysis Engineer
4 weeks ago
Bengaluru, Karnataka, India Capgemini Engineering Full timeJob Description Key Responsibilities: Timing Analysis & Closur e Perform setup, hold, and skew analysis across Full-Chip, Sub-system, and IP levels. Achieve timing closure by resolving violations and optimizing paths. Constraint Development Define and validate timing constraints (clocks, I/O delays, false/multi-cycle paths). Integrate...
