Static Timing Analysis

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You are an accomplished engineering professional with a passion for cutting-edge semiconductor innovation and a proven track record in static timing analysis (STA) and backend design implementation. With at least 8 years of industry experience, you bring deep expertise in STA concepts, tools, and methodologies across IP, subsystem, and full-chip levels. You thrive on tackling complex challenges, such as timing closure and signoff processes at advanced nodes (from 16nm down to 3nm and beyond), and are adept at synthesizing intricate designs into robust, high-performance silicon solutions.

Your technical acumen is complemented by your ability to lead and mentor cross-functional teams, communicate effectively with internal stakeholders and external customers, and drive projects to successful tape-outs. You are energized by collaborative environments that value innovation, continuous learning, and diversity of thought. Your approach is detail-oriented and systematic, ensuring that each phase of the design flow—from RTL to GDSII—meets the highest standards of quality and efficiency. You are eager to contribute to Synopsys' mission of empowering the next generation of smart, connected devices through your expertise in STA, physical design, and IP integration.

• Leading STA activities for SLM IPs and subsystems, including planning, execution, and review of timing analysis tasks.
• Developing and maintaining STA checkers and methodologies for advanced process nodes (16nm to 3nm and beyond).
• Collaborating with design and verification teams to ensure seamless integration of timing constraints and closure strategies.
• Driving synthesis, pre-layout and post-layout STA, and clock tree synthesis (CTS) to achieve optimal performance and power targets.
• Managing timing closure in multi-corner, multi-mode environments, including functional, DFT, and at-speed constraints.
• Generating engineering change orders (ECOs) for design rule violation (DRV) cleaning and timing closure, ensuring successful tape-outs.
• Enhancing design flows by developing custom scripts (TCL/PERL) and automating STA processes for improved efficiency.

• Driving successful timing closure and signoff for state-of-the-art SLM controllers and on-chip monitors.
• Enabling robust, high-performance IP and subsystem designs at the most advanced silicon nodes.
• Ensuring reliability and predictability of silicon by implementing best-in-class STA methodologies.
• Reducing time-to-market through efficient planning, execution, and automation of backend flows.
• Mentoring junior engineers and fostering a culture of technical excellence and continuous improvement.
• Collaborating with global teams to deliver differentiated products that set industry benchmarks in performance and power.
• Elevating Synopsys' reputation as a leader in hardware analytics and test solutions through successful customer engagements and tape-outs.

• BS or MS degree in Electrical Engineering or related discipline, with 8+ years of relevant industry experience.
• Expertise in STA concepts, tools, and methodologies at IP, subsystem, and chip levels.
• Hands-on experience with synthesis, pre-layout and post-layout STA, CTS, and signoff flows.
• Proficiency in backend implementation using industry-standard EDA tools, preferably Synopsys PrimeTime, ICC2, Design Compiler, Fusion Compiler, or equivalents.
• Strong knowledge of RTL2GDSII flows, including place & route, timing closure, EMIR, and layout closure.
• Experience developing timing constraints for functional, DFT, and multi-mode designs, with proven success in tape-outs at advanced nodes (14nm, 10nm, 7nm, 5nm, 3nm, 2nm).
• Skill in custom scripting (TCL/PERL) for flow automation and improvement.

• Innovative problem-solver with keen attention to detail and a systematic approach.
• Excellent communicator, able to translate complex technical concepts to diverse audiences.
• Collaborative teammate, skilled at working in global, cross-functional environments.
• Empathetic mentor, eager to share knowledge and foster team growth.
• Adaptable and resilient, thriving in fast-paced, dynamic settings
• Committed to continuous learning and professional development.

You will join the dynamic Hardware-Analytics and Test (HAT) business unit, specifically the SLM Hardware Group, an innovative team at the forefront of developing next-generation SLM controllers, on-chip monitors, and infrastructure IPs. Our team is passionate about solving complex technical challenges, driving product differentiation, and delivering industry-leading solutions in hardware analytics and testing. You'll collaborate with talented engineers, architects, and product managers across global locations, contributing to a culture of excellence, inclusion, and continuous innovation.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.