Static Timing Analysis Engineer SI50FT RM 3681

Position: Static Timing Analysis Engineer (SI50FT RM 3681)Job DescriptionSTA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.Timing analysis, validation and debug across multiple PVT conditions using Tempus.Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.Hands-on experience with STA...

Position: Physical Design Engineer with Innovus skills (SI50FT RM 3680)Job DescriptionSolid experience in place & route flow (placement guidelines, clock-tree synthesis, routing, timing optimizations).Experience on hierarchical designs and/or Low Power implementation is an advantage.Experience on Synthesis, interfacing with RTL and implementationExperience...

Position: Physical Design Engineer with Innovus skills (SI50FT RM 3680)Job descriptionSolid experience in place & route flow (placement guidelines, clock-tree synthesis, routing, timing optimizations).Experience on hierarchical designs and/or Low Power implementation is an advantage.Experience on Synthesis, interfacing with RTL and implementationExperience...

Position: Design verification (SI50FT RM 3603)Responsibilities & Required Experience:Define test plan/design, test cases, and develop test scripts for RPG product validation.Collaborate with architecture and design teams to define validation flows.Experience in PHY verification and high-speed blocks with IOs.Run and debug gate-level simulations.Familiarity...

Position: Engineer with CLP & UPF expertise (SI50FT RM 3638)Job Description & Skill Requirement.Strong understanding of low-power design concepts- power domains, isolations, retention, level shifters, power gating. etc.Run and debug Conformal Low Power (CLP) checks at various stages (RTL vs UPF, Gate-level vs UPF, etc.).Identify and resolve power domain...

Hi Folks,Please find here JD for your reference.Work Location: BangaloreStatic Timing Analysis Engineer – Exp 8 yrs and higher.Job description :1.    STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.2.    Timing analysis, validation and debug across multiple PVT conditions using Tempus or Primetime at chip...

Description : Job Title : STA Engineer Location : Bangalore, India Experience : 4 yearsJob Overview : We are seeking a highly skilled Design Verification and Static Timing Analysis (STA) Engineer with expertise in scan, ATPG, and SV UVM methodologies, as well as pre- and post-layout STA. The ideal candidate will be responsible for ensuring the...

Key Skills: Static Timing Analysis,PrimeTimeRoles and Responsibilities:Conduct block-level and full-chip static timing analysis across all phases of development.Develop timing methodologies and infrastructure from RTL synthesis to timing closure.Collaborate with architects and designers to define block and chip-level timing constraints.Define analysis...

Static Timing Analysis (STA) EngineerJob Summary The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with design and...

Static Timing Analysis (STA) Engineer Job DescriptionJob SummaryThe Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with...