Static Timing Analysis

1 day ago

Bengaluru, Karnataka, India Eduplex services private limited Full time ₹ 20,00,000 - ₹ 30,00,000 per year

Static Timing Analysis (STA) Lead

Location: Bangalore, KA

Experience: 7–18 Years

Budget: Up to 30 LPA (DoE)

Industry: Semiconductors | ASIC | SoC | AI/Networking Chips

Job Type: Full-Time

Job Overview

We are seeking a highly skilled Static Timing Analysis (STA) Lead to drive timing closure for large-scale, high-performance ASIC/SoC designs. The ideal candidate will have deep expertise in STA concepts, tools, and methodologies, along with a proven track record of working on advanced FinFET nodes. This role demands both strong technical problem-solving abilities and leadership skills to guide teams through complex timing challenges.

Key Responsibilities

  • Lead STA efforts for complex ASIC/SoC designs across multiple blocks and hierarchies.
  • Define and implement robust STA methodologies, ensuring consistency across projects.
  • Develop, validate, and optimize SDC constraints for multiple modes and corners.
  • Perform comprehensive multi-mode, multi-corner (MMMC) analysis, addressing setup/hold, recovery/removal, pulse width, and other timing checks.
  • Drive signal integrity (SI), noise analysis, and crosstalk mitigation for reliable timing closure.
  • Apply AOCV, POCV, LVF, and statistical timing techniques on advanced process nodes.
  • Collaborate closely with RTL, synthesis, place-and-route, and verification teams to debug and resolve timing issues.
  • Automate STA flows, reporting, and analysis using TCL, Perl, or Python scripting.
  • Mentor junior engineers and provide technical leadership in STA best practices.
  • Interface with EDA vendors to resolve tool-related issues and influence enhancements.

Required Skills & Qualifications

  • Education: Bachelor's/Master's degree in Electrical Engineering, Computer Engineering, or related field.
  • Experience: 7–18+ years of proven hands-on experience in STA and timing closure for complex SoCs/ASICs.
  • Tool Expertise: Advanced knowledge of Synopsys PrimeTime (PT); familiarity with alternative STA tools is a plus.
  • Technical Expertise:
  • SDC creation and constraint validation.
  • Crosstalk, noise analysis, and mitigation techniques.
  • On-Chip Variation handling (AOCV, POCV, LVF).
  • Deep knowledge of clock/data path analysis and MMMC flows.
  • Scripting: Expert in TCL, with additional proficiency in Perl and/or Python for automation.
  • Technology Nodes: Hands-on experience with FinFET technologies (16nm, 7nm, 5nm, or below) is highly desirable.
  • Problem-Solving: Strong analytical/debugging skills with the ability to independently resolve timing closure challenges.
  • Communication: Excellent communication and collaboration skills to work effectively with global, cross-functional teams.

Preferred Qualifications

  • Master's or PhD in Electrical Engineering, Computer Engineering, or a related field.
  • Prior experience leading STA teams in top-tier semiconductor or product-based companies.

Job Types: Full-time, Permanent

Pay: Up to ₹3,000,000.00 per year

Benefits:

  • Health insurance
  • Life insurance
  • Provident Fund

Experience:

  • top-tier semiconductor or product-based companies: 7 years (Required)

Work Location: In person

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