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Senior Timing Closure Engineer
3 weeks ago
Lead synthesis and static timing analysis efforts for a cutting-edge mixed signal chip.
About the RoleThis highly visible position is at the heart of Soc design, interfacing with various disciplines to ensure timely product delivery. You will be part of a talented team responsible for providing integrated solutions into a growth industry.
Key Responsibilities- Closure ownership throughout the project cycle (RTL, synthesis, and physical implementation).
- Development and maintenance of methodology and flows related to timing verification and closure.
- Generation of block and full chip timing constraints.
- Analysis of timing reports and utilization of scripting techniques to develop insights and drive rapid timing closure.
- Support for digital chip integration work and flows.
- Bachelor's/Master's/PhD degree with at least 6+ years hands-on experience in ASIC timing constraints generation and timing closure.
- Expertise in STA tools (Tempus and Primetime) and methodologies for timing closure with a good understanding of OCV, noise, and crosstalk effects on timing.
- Familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced finFET technology nodes, preferably 7nm.
- Knowledge of timing corners/modes and process variations.
- Knowledge of low-power techniques including clock gating, power gating, and millivoltage designs. Proficiency in scripting languages (Tcl and Perl).
- Strong communication skills are required as the candidate will interface with various groups.
- Familiarity with RTL, synthesis, logic equivalence, DFT, floor-planning, and backend-related methodology and tools.
- Able to solve complex problems and independently drive tasks to completion in a timely manner.
- Work on leading edge technologies.
- An opportunity for career development and growth.
- Competitive compensation.
- Medical benefits and more.
