Timing Closure Expert
2 days ago
We are seeking a highly skilled Staff Design Engineer/Design Manager to lead the synthesis, static timing and DFT efforts for an advanced mixed signal chip.
- Key Responsibilities:
- Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation).
- Develop and maintain methodology and flows related to timing verification and closure.
- Generation of block and full chip timing constraints.
- Analyze timing reports and utilize scripting techniques to develop insights and drive rapid ECO timing closure.
About the Role:
- The position requires thorough knowledge of the ASIC design timing closure flow and methodology.
- Expertise in STA tools (Tempus and Primetime) and methodologies for timing closure with a good understanding of OCV, noise and crosstalk effects on timing.
- Familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced finFET technology nodes, preferably 7nm.
- Knowledge of timing corners/modes and process variations.
- Knowledge of low-power techniques including clock gating, power gating and millivoltage designs. Proficient in scripting languages (Tcl and Perl).
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