Senior Static Timing and Place and Route Engineer

3 days ago

Tirupati, Andhra Pradesh, India beBeeStaticTimingAnalysis Full time ₹ 1,50,00,000 - ₹ 2,50,00,000
Senior Static Timing and Place and Route Engineer

We are seeking an experienced Senior Static Timing and Place and Route (STA/PNR) engineer to join our team.

About the Role:

This is a senior-level position that requires expertise in STA and PNR for complex subsystems within ASIC/SoC design, including advanced technology nodes.

The ideal candidate will have extensive experience with STA tools such as Synopsys PrimeTime and Cadence Tempus, as well as PNR tools like Synopsys ICC2 and Cadence Innovus.

Key Responsibilities:

  • Lead STA and PNR activities for complex subsystems, ensuring robust timing closure and physical implementation with a focus on power, performance, and area optimization.
  • Develop and refine methodologies for STA and PNR tailored to the unique challenges of large, multi-interface, or mixed-signal subsystems.
  • Drive automation and validation of timing and physical design data across subsystem boundaries.
  • Mentor and guide junior engineers, fostering technical growth and knowledge sharing within subsystem teams.
  • Collaborate cross-functionally to resolve design, timing, and physical implementation challenges specific to complex subsystem integration.

Qualifications and Skills:

  • 10+ years of experience in STA and PNR for complex subsystems within ASIC/SoC design, including advanced technology nodes.
  • Demonstrated expertise in STA tools and PNR tools applied to large, multi-block or hierarchical subsystems.
  • Proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems.
  • Proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows across multiple subsystem blocks.
  • Deep understanding of SoC design flows, with experience collaborating across frontend, physical design, and verification teams to integrate complex subsystems.
  • Experience with IP collateral generation and quality assurance for timing and physical design at the subsystem level preferred.
  • Background in high-speed interfaces, or mixed-signal SoC subsystems.

Benefits:

This role offers a competitive salary, comprehensive benefits package, and opportunities for professional growth and development.

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