
Senior ASIC Physical Design Engineer
5 days ago
Seeking a Physical Design Expert to join our team.
Job Description:
- Achieve comprehensive physical design solutions for Fullchip/Blocks encompassing Floorplanning, Placement, Budgeting, Clock Tree planning & analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, Low Power solution development & implementation.
- Possess in-depth knowledge of EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, internal tools & flow, etc.
- Collaborate closely with the methodology team to resolve implementation challenges & contribute inputs to enhance the Physical design flow.
- Proven expertise in design automation.
- Understand Timing constraints, SI prevention, Power reduction.
- Must have prior experience with Synopsys/Cadence/Mentor place and route tools.
- Must have completed design in 16nm and or 7nm.
- Familiarity with Unix/TCL/Perl.
Required Skills & Qualifications:
- 4+ years experience in ASIC physical design
- Experience with block implementation, extraction, timing and or full-chip designs
- Strong communication skills
- Strong hands-on TCL/Perl development skills
Benefits:
- Opportunity to work on complex chip designs
- Chance to develop Low Power solutions
- Collaborative work environment
Others:
- Will be responsible for leading teams
- Should be able to analyze complex data
- Must be proficient in presentation skills
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