Senior Digital Test Engineer

15 hours ago

Tirupati, Andhra Pradesh, India beBeeDigitalTest Full time ₹ 1,00,00,000 - ₹ 1,50,00,000
Job Title: Senior Digital Test Engineer

Description:

We are seeking a seasoned digital test engineer to drive the development and implementation of digital testing strategies for complex SoC/ASIC designs.

Key Responsibilities:

  • Develop and execute digital test plans and strategies for multiple ASIC/SoC projects.
  • Lead the design, implementation, and verification of digital test features like scan insertion and compression, ATPG pattern generation and fault grading, MBIST and Logic BIST insertion and validation, boundary scan (IEEE 1149.1/1149.6), IJTAG (1687).
  • Manage the end-to-end digital test flow from RTL to gate-level netlist and silicon bring-up.
  • Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.
  • Perform pattern generation, fault simulation, and debug test coverage gaps.
  • Ensure digital test signoff, timing closure (DFT-related paths), and ATE pattern delivery.
  • Support silicon bring-up, test vector validation on ATE, and yield optimization.
  • Mentor and guide junior DFT engineers; conduct design reviews and training sessions.
  • Develop and maintain digital test automation scripts and infrastructure.

Requirements:

  • B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.
  • 7+ years of experience in digital test for complex ASIC or SoC designs.
  • Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.
  • Hands-on experience with digital test tools such as Synopsys, Siemens EDA, Cadence/others.
  • Strong knowledge of RTL design, STA, and synthesis flows.
  • Proficient in scripting languages (Python, Perl, Tcl) for flow automation.
  • Deep understanding of silicon test challenges and test coverage improvement.
  • Strong leadership, team collaboration, and communication skills.

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