Senior/Lead STA engineer

We're Hiring: STA Engineer | 5–10 Years Experience | Bangalore & HyderabadCompany: Wafer Space – An ACL Digital CompanyLocation: Bangalore & HyderabadExperience: 5 to 15 YearsJob Type: Full-TimeWafer Space, a leading VLSI design services company and part of ACL Digital , is looking for Senior Static Timing Analysis (STA) Engineers with solid...

We're Hiring: STA Engineer | 5–10 Years Experience | Bangalore & HyderabadCompany:ACL Digital CompanyLocation:Bangalore & HyderabadExperience:5 to 15 YearsJob Type:Full-TimeACL Digitalis looking forSenior Static Timing Analysis (STA) Engineerswith solid experience in timing closure of advanced SoC designs.If you're an STA expert who thrives in fast-paced,...

We're Hiring: STA Engineer | 5–10 Years Experience | Bangalore & Hyderabad Company: ACL Digital Company Location: Bangalore & Hyderabad Experience: 5 to 15 Years Job Type: Full-Time ACL Digital is looking for Senior Static Timing Analysis (STA) Engineers with solid experience in timing closure of advanced SoC designs. If you're an STA expert who...

We're Hiring: STA Engineer | 5–10 Years Experience | Bangalore & HyderabadCompany: ACL Digital CompanyLocation: Bangalore & HyderabadExperience: 5 to 15 YearsJob Type: Full-TimeACL Digital is looking for Senior Static Timing Analysis (STA) Engineers with solid experience in timing closure of advanced SoC designs.If you're an STA expert who thrives in...

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill...

Job DescriptionKey Responsibilities:Timing Analysis & ClosurePerform setup, hold, and skew analysis across Full-Chip, Sub-system, and IP levels.Achieve timing closure by resolving violations and optimizing paths.Constraint DevelopmentDefine and validate timing constraints (clocks, I/O delays, false/multi-cycle paths).Integrate constraints from multiple IPs...

Full-Chip STA EngineerWe are seeking an experienced Full-Chip STA Engineer to drive timing closure and sign-off across the entire SoC/ASIC design. The role requires expertise in multi-block integration, multi-mode/multi-corner analysis, and sign-off methodology for advanced technology nodes.Key Responsibilities : - Perform full-chip static timing analysis...

Are you passionate about driving performance at the silicon level? We are looking for an experienced STA Engineer with 5 years of expertise in Static Timing Analysis (STA) to join our team Key Responsibilities:Perform timing analysis, validation, and debug across multiple PVT corners using Tempus Hands-on experience with Tempus DMMMC flow for STA ...

Looking for STA Engineer.Exp.-5+yrs.Job Location- Bangalore/Hyderabad/remote.Notice Period- Prefer Immediate joiner or less notice period.- Netlist and constraint sign in checks and validation.- Prime time constraint generation/development at Top level, full chip level and clean up.- Multimode multi corner timing knowledge and timing closure at sub...

Role & responsibilitiesDevelop, validate, and maintain STA constraints (SDC) for multiple design modes and corners (functional, test, scan, BIST, low power, etc.).Own DFT timing constraints (scan shift, capture, at-speed test, boundary scan, MBIST, LBIST, JTAG).Collaborate with DFT and Physical Design teams to ensure test structures meet timing closure...