
Senior/Lead STA engineer
4 days ago
• Own and drive timing closure for complex SoC and ASIC designs across multiple technology nodes
• Perform full-chip and block-level timing analysis using industry-standard tools (Primetime, Tempus, etc.)
• Collaborate with RTL, synthesis, physical design, and verification teams to resolve timing violations
• Develop and maintain timing constraints (SDC), run STA checks (setup, hold, DRV, SI), and support ECO timing closure
• Contribute to methodology improvements and timing signoff strategies
• Report timing status, risks, and closure plans to technical leads and project stakeholdersRequired Skills & Experience:
• 5–10 years of solid hands-on experience in STA and timing closure
• Strong expertise in timing concepts, constraints development, and signoff methodology
• Proficient in tools like Synopsys Primetime, Cadence Tempus
• Solid understanding of clock tree design, DFT, multi-mode multi-corner (MMMC) analysis
• Good scripting skills (TCL/Perl/Python) to automate and debug flows
• Experience with advanced nodes (7nm/5nm/FinFET) is a plus
• Strong analytical, problem-solving, and communication skillsWhy Join Wafer Space?
• Be part of a high-growth, innovation-driven semiconductor company
• Work on state-of-the-art technologies with leading global clients
• Collaborative and empowering work culture
• Competitive compensation and flexible work options
• Opportunity to grow your career in a technically challenging environmentInterested?Send your resume to
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Senior/Lead STA engineer
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Senior/Lead STA engineer
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Senior/Lead STA engineer
4 weeks ago
Bengaluru, Karnataka, India Wafer Space - An ACL Digital Company Full timeWe're Hiring: STA Engineer | 5–10 Years Experience | Bangalore & Hyderabad Company: Wafer Space – An ACL Digital Company Location: Bangalore & Hyderabad Experience: 5 to 15 Years Job Type: Full-Time Wafer Space, a leading VLSI design services company and part of ACL Digital , is looking for Senior Static Timing Analysis (STA) Engineers with solid...
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3 Days Left Senior/Lead STA engineer
4 weeks ago
Bengaluru, Karnataka, India Wafer Space - An ACL Digital Company Full timeWe're Hiring: STA Engineer | 5–10 Years Experience | Bangalore & HyderabadCompany: Wafer Space – An ACL Digital CompanyLocation: Bangalore & HyderabadExperience: 5 to 15 YearsJob Type: Full-TimeWafer Space, a leading VLSI design services company and part of ACL Digital, is looking for Senior Static Timing Analysis (STA) Engineers with solid experience in...
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STA Lead
2 weeks ago
Bengaluru, Karnataka, India Xanika Infotech Full timeFull-Chip STA EngineerWe are seeking an experienced Full-Chip STA Engineer to drive timing closure and sign-off across the entire SoC/ASIC design. The role requires expertise in multi-block integration, multi-mode/multi-corner analysis, and sign-off methodology for advanced technology nodes.Key Responsibilities : - Perform full-chip static timing analysis...
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Senior/Staff STA Engineer
4 weeks ago
Bengaluru, Karnataka, India Tenstorrent Full timeTenstorrent is looking for a skilled and detail-oriented Static Timing Analysis (STA) Engineer to help us deliver first-pass silicon success for our cutting-edge AI and RISC-V SoCs. Engineers with a strong foundation in Static Timing Analysis (STA) and timing constraints . In this role, you'll lead timing closure efforts across block and full-chip levels,...
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STA Engineer
3 hours ago
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STA Engineer
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STA Engineer
19 hours ago
Bengaluru, Karnataka, India ACL Digital Full timeLooking for STA Engineer. Exp.-5+yrs. Job Location- Bangalore/Hyderabad/remote. Notice Period- Prefer Immediate joiner or less notice period. Netlist and constraint sign in checks and validation. Prime time constraint generation/development at Top level, full chip level and clean up. Multimode multi corner timing knowledge and timing closure at sub...
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Senior/Staff STA Engineer
2 weeks ago
Bengaluru, Karnataka, India Tenstorrent Full timeTenstorrent is looking for a skilled and detail-oriented Static Timing Analysis (STA) Engineer to help us deliver first-pass silicon success for our cutting-edge AI and RISC-V SoCs. Engineers with a strong foundation in Static Timing Analysis (STA) and timing constraints . In this role, you'll lead timing closure efforts across block and full-chip levels,...