Senior/Lead STA engineer

We're Hiring: STA Engineer | 5–10 Years Experience | Bangalore & HyderabadCompany:ACL Digital CompanyLocation:Bangalore & HyderabadExperience:5 to 15 YearsJob Type:Full-TimeACL Digitalis looking forSenior Static Timing Analysis (STA) Engineerswith solid experience in timing closure of advanced SoC designs.If you're an STA expert who thrives in fast-paced,...

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill...

Minimum Qualifications:Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work...

Job Title: STA EngineerLocation: Banglaore/HyderabadEmployment Type: Full-timeIndustry: Semiconductors / VLSI / ASIC DesignJob Summary:We are looking for a skilled and motivated STA Engineer to join our backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, targeting...

Job DescriptionKey Responsibilities:Timing Analysis & ClosurePerform setup, hold, and skew analysis across Full-Chip, Sub-system, and IP levels.Achieve timing closure by resolving violations and optimizing paths.Constraint DevelopmentDefine and validate timing constraints (clocks, I/O delays, false/multi-cycle paths).Integrate constraints from multiple IPs...

Static Timing Analysis (STA) EngineerJob SummaryThe Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with design and...

Role & responsibilitiesDevelop, validate, and maintain STA constraints (SDC) for multiple design modes and corners (functional, test, scan, BIST, low power, etc.).Own DFT timing constraints (scan shift, capture, at-speed test, boundary scan, MBIST, LBIST, JTAG).Collaborate with DFT and Physical Design teams to ensure test structures meet timing closure...

STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs. Timing analysis, validation and debug across multiple PVT conditions using Tempus. Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. Hands-on experience with STA tools - Tempus In-depth knowledge cross-talk noise, Signal Integrity,...

Looking for STA Engineer.Exp.-5+yrs.Job Location- Bangalore/Hyderabad/remote.Notice Period- Prefer Immediate joiner or less notice period.Netlist and constraint sign in checks and validation.Prime time constraint generation/development at Top level, full chip level and clean up.Multimode multi corner timing knowledge and timing closure at sub HM/block/top...

Looking for STA Engineer.Exp.-5+yrs.Job Location- Bangalore/Hyderabad/remote.Notice Period- Prefer Immediate joiner or less notice period.Netlist and constraint sign in checks and validation.Prime time constraint generation/development at Top level, full chip level and clean up.Multimode multi corner timing knowledge and timing closure at sub HM/block/top...