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Senior STA Engineer
2 weeks ago
Role & responsibilities
Develop, validate, and maintain STA constraints (SDC) for multiple design modes and corners (functional, test, scan, BIST, low power, etc.).
- Own DFT timing constraints (scan shift, capture, at-speed test, boundary scan, MBIST, LBIST, JTAG).
- Collaborate with DFT and Physical Design teams to ensure test structures meet timing closure requirements.
- Work with synthesis, P&R, and STA teams to merge functional and test-mode constraints consistently.
- Debug timing violations across functional and DFT modes, and propose fixes (false paths, multicycle paths, case analysis, test clocks).
- Ensure SDC quality by writing scripts/checkers for constraint consistency, redundancy, and coverage.
- Interface with ATPG teams to validate scan patterns with timing intent.
- Participate in signoff STA, including test modes, to ensure tapeout quality.
Desired Skills:
- Strong expertise in STA constraint development and debugging.
- Hands-on experience with SDC, DFT constraints, and signoff STA tools.
- Good scripting skills for automation and validation.
- Excellent collaboration skills across cross-functional teams.
