Lead STA

3 days ago

bangalore district, India Cadence System Design and Analysis Full time

BE /Btech EXp- 5- 12 Yrs Work on challenging DDR PHY IP & Testchip Physical Design from Netlist-to-GDS in tech nodes below 7nm. • Take ownership of one or more physical design blocks includes all of, floorplan, CTS, PNR, QRC, STA, PV & IR. • Contribute to design methodology, flow automation. • Innovate & implement Power, Performance and Area optimization techniques. • Participate in IP release to customers and support team on standardize & document learnings. Key Skills: Netlist-GDS physical design, 7nm+ Technology nodes, CTS and Custom Clocking, STA, PV, scripting tcl & python. Minimum qualifications: • Bachelor’s degree in Electronics or equivalent practical experience. • 3+ years of experience and in depth knowledge on Netlist-GDS physical design. • Experience on sub 7nm tech nodes. • Good hands on experience on scripting tcl & python. Preferred qualifications: • Experience in hardening DDR PHY designs. • Experience in physical synthesis and constraints design. • Experience in Cadence tools Innovus, Genus, Tempus & Voltus. • Experience in RDL routing, PERC ESD checks. • Lower Tech node N3, Samsung N5,N4 knowledge is a plus.

  • Senior/Lead STA engineer

    1 week ago

    bangalore district, India ACL Digital Full time

    We’re Hiring: STA Engineer | 5–15 Years Experience | Bangalore Company: ACL Digital Company Location: Bangalore Experience: 5 to 15 Years Job Type: Full-Time ACL Digital is looking for Senior Static Timing Analysis (STA) Engineers with solid experience in timing closure of advanced SoC designs. If you’re an STA expert who thrives in fast-paced,...

  • Senior STA Architect

    1 week ago

    bangalore district, India Eximietas Design Full time

    Hello All, Eximietas Design Hiring STA Engineers/Leads Experience: 8+ Years. Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA. Anyone with a Valid H1B or Already in US. Job Description: Experience in Static Timing Analysis (STA) for ASIC designs. Experience in developing timing constraints. Experience in timing closure and...

  • Senior/Lead STA engineer

    1 week ago

    Bangalore, India ACL Digital Full time

    We’re Hiring: STA Engineer | 5–15 Years Experience | Bangalore Company: ACL Digital Company Location: Bangalore Experience: 5 to 15 Years Job Type: Full-Time ACL Digital is looking for Senior Static Timing Analysis (STA) Engineers with solid experience in timing closure of advanced SoC designs. If you’re an STA expert who thrives in fast-paced,...

  • Senior/Lead STA engineer

    1 week ago

    bangalore, India ACL Digital Full time

    We’re Hiring: STA Engineer | 5–15 Years Experience | BangaloreCompany: ACL Digital CompanyLocation: BangaloreExperience: 5 to 15 YearsJob Type: Full-TimeACL Digital is looking for Senior Static Timing Analysis (STA) Engineers with solid experience in timing closure of advanced SoC designs.If you’re an STA expert who thrives in fast-paced, technically...

  • Senior/Lead STA engineer

    5 days ago

    Bangalore Division, India ACL Digital Full time

    We’re Hiring: STA Engineer | 5–15 Years Experience | Bangalore Company: ACL Digital Company Location: Bangalore Experience: 5 to 15 Years Job Type: Full-Time ACL Digital is looking for Senior Static Timing Analysis (STA) Engineers with solid experience in timing closure of advanced SoC designs. If you’re an STA expert who thrives in fast-paced,...

  • STA Lead

    5 days ago

    bangalore, India ACL Digital Full time

    Technical Skills:Well versed with the timing closure (STA), timing closure methodologies.Pre/Post-layout constraint development to timing closure.Handshake with the design team and develop functional/DFT constraints.IP level constraint integration.Multi-voltage/Switching aware corner definitions.RC/C model selection understanding.Abstraction expertise like...

  • STA Lead

    5 days ago

    bangalore, India ACL Digital Full time

    Technical Skills: Well versed with the timing closure (STA), timing closure methodologies. Pre/Post-layout constraint development to timing closure. Handshake with the design team and develop functional/DFT constraints. IP level constraint integration. Multi-voltage/Switching aware corner definitions. RC/C model selection understanding. Abstraction expertise...

  • Senior STA Architect

    1 week ago

    Bangalore, India Eximietas Design Full time

    Hello All, Eximietas Design Hiring STA Engineers/Leads Experience: 8+ Years. Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA. Anyone with a Valid H1B or Already in US. Job Description: Experience in Static Timing Analysis (STA) for ASIC designs. Experience in developing timing constraints. Experience in timing closure and...

  • Lead STA

    5 days ago

    bangalore, India Cadence System Design and Analysis Full time

    BE /BtechEXp- 5- 12 YrsWork on challenging DDR PHY IP & Testchip Physical Design from Netlist-to-GDS in tech nodes below 7nm.• Take ownership of one or more physical design blocks includes all of, floorplan, CTS, PNR, QRC, STA, PV & IR.• Contribute to design methodology, flow automation.• Innovate & implement Power, Performance and Area optimization...

  • Lead STA

    5 days ago

    Bangalore, India Cadence System Design and Analysis Full time

    BE /Btech EXp- 5- 12 Yrs Work on challenging DDR PHY IP & Testchip Physical Design from Netlist-to-GDS in tech nodes below 7nm. • Take ownership of one or more physical design blocks includes all of, floorplan, CTS, PNR, QRC, STA, PV & IR. • Contribute to design methodology, flow automation. • Innovate & implement Power, Performance and Area...