Lead STA
2 weeks ago
BE /BtechEXp- 5- 12 YrsWork on challenging DDR PHY IP & Testchip Physical Design from Netlist-to-GDS in tech nodes below 7nm.• Take ownership of one or more physical design blocks includes all of, floorplan, CTS, PNR, QRC, STA, PV & IR.• Contribute to design methodology, flow automation.• Innovate & implement Power, Performance and Area optimization techniques.• Participate in IP release to customers and support team on standardize & document learnings.Key Skills: Netlist-GDS physical design, 7nm+ Technology nodes, CTS and Custom Clocking, STA, PV, scripting tcl & python.Minimum qualifications:• Bachelor’s degree in Electronics or equivalent practical experience.• 3+ years of experience and in depth knowledge on Netlist-GDS physical design.• Experience on sub 7nm tech nodes.• Good hands on experience on scripting tcl & python.Preferred qualifications:• Experience in hardening DDR PHY designs.• Experience in physical synthesis and constraints design.• Experience in Cadence tools Innovus, Genus, Tempus & Voltus.• Experience in RDL routing, PERC ESD checks.• Lower Tech node N3, Samsung N5,N4 knowledge is a plus.
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Senior/Lead STA engineer
2 weeks ago
Bangalore Division, India ACL Digital Full timeWe’re Hiring: STA Engineer | 5–15 Years Experience | Bangalore Company: ACL Digital Company Location: Bangalore Experience: 5 to 15 Years Job Type: Full-Time ACL Digital is looking for Senior Static Timing Analysis (STA) Engineers with solid experience in timing closure of advanced SoC designs. If you’re an STA expert who thrives in fast-paced,...
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STA Lead
2 weeks ago
bangalore, India ACL Digital Full timeTechnical Skills:Well versed with the timing closure (STA), timing closure methodologies.Pre/Post-layout constraint development to timing closure.Handshake with the design team and develop functional/DFT constraints.IP level constraint integration.Multi-voltage/Switching aware corner definitions.RC/C model selection understanding.Abstraction expertise like...
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STA Lead
2 weeks ago
bangalore, India ACL Digital Full timeTechnical Skills: Well versed with the timing closure (STA), timing closure methodologies. Pre/Post-layout constraint development to timing closure. Handshake with the design team and develop functional/DFT constraints. IP level constraint integration. Multi-voltage/Switching aware corner definitions. RC/C model selection understanding. Abstraction expertise...
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Lead STA
2 weeks ago
Bangalore, India Cadence System Design and Analysis Full timeBE /Btech EXp- 5- 12 Yrs Work on challenging DDR PHY IP & Testchip Physical Design from Netlist-to-GDS in tech nodes below 7nm. • Take ownership of one or more physical design blocks includes all of, floorplan, CTS, PNR, QRC, STA, PV & IR. • Contribute to design methodology, flow automation. • Innovate & implement Power, Performance and Area...
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Lead STA
1 week ago
bangalore district, India Cadence System Design and Analysis Full timeBE /Btech EXp- 5- 12 Yrs Work on challenging DDR PHY IP & Testchip Physical Design from Netlist-to-GDS in tech nodes below 7nm. • Take ownership of one or more physical design blocks includes all of, floorplan, CTS, PNR, QRC, STA, PV & IR. • Contribute to design methodology, flow automation. • Innovate & implement Power, Performance and Area...
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Bangalore, Karnataka, India Qualcomm Full timeCompany Qualcomm India Private Limited Job Area Engineering Group Engineering Group Hardware Engineering General Summary As a leading technology innovator Qualcomm pushes the boundaries of what s possible to enable next-generation experiences and drives digital transformation to help create a smarter connected future for all As a Qualcomm Hardware Engineer...
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Bangalore, Bengaluru, Hyderabad, India Newsoft Consultants Full time ₹ 12,00,000 - ₹ 36,00,000 per year• SoC/Blocks Synthesis/STA methodology & flow for meeting PPA goals• Work with Backend team in realizing PPA goals during PnR & IP & SoC Design team in optimizing the design to meet PPA goals.• Feedback on design issues & solutions. Required Candidate profile• Exp in front end design implementation.• Design flows like Synthesis, Constraint Devel.,...
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15h Left! Soc Sta/timing Engineer
6 days ago
Bangalore, Karnataka, India Qualcomm Full timeCompany Qualcomm India Private Limited Job Area Engineering Group Engineering Group Hardware Engineering General Summary As a leading technology innovator Qualcomm pushes the boundaries of what s possible to enable next-generation experiences and drives digital transformation to help create a smarter connected future for all As a Qualcomm Hardware Engineer...
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Soc Sta/timing Engineer
4 weeks ago
Bangalore, Karnataka, India Qualcomm Full timeCompany Qualcomm India Private Limited Job Area Engineering Group Engineering Group Hardware Engineering General Summary As a leading technology innovator Qualcomm pushes the boundaries of what s possible to enable next-generation experiences and drives digital transformation to help create a smarter connected future for all As a Qualcomm Hardware Engineer...
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Static Timing Analysis Lead
4 weeks ago
Bangalore, Karnataka, India Cloudious Full timeJob Title Static Timing Analysis Lead Location Bengaluru India Experience 7 18 years Industry Semiconductors AI Networking ASIC Design Role Overview We re looking for an experienced and driven Static Timing Analysis STA and Timing Signoff Methodology lead In this role you ll be the expert responsible for defining developing and maintaining the entire STA...
