Senior/lead sta engineer
5 days ago
We’re Hiring: STA Engineer | 5–10 Years Experience | Bangalore & Hyderabad Company: ACL Digital Company Location: Bangalore & Hyderabad Experience: 5 to 15 Years Job Type: Full-Time ACL Digital is looking for Senior Static Timing Analysis (STA) Engineers with solid experience in timing closure of advanced So C designs. If you’re an STA expert who thrives in fast-paced, technically challenging environments, we want to hear from you Responsibilities: • Own and drive timing closure for complex So C and ASIC designs across multiple technology nodes • Perform full-chip and block-level timing analysis using industry-standard tools (Primetime, Tempus, etc.)• Collaborate with RTL, synthesis, physical design, and verification teams to resolve timing violations • Develop and maintain timing constraints (SDC), run STA checks (setup, hold, DRV, SI), and support ECO timing closure • Contribute to methodology improvements and timing signoff strategies • Report timing status, risks, and closure plans to technical leads and project stakeholders Required Skills & Experience: • 5–10 years of solid hands-on experience in STA and timing closure • Strong expertise in timing concepts, constraints development, and signoff methodology • Proficient in tools like Synopsys Primetime, Cadence Tempus • Solid understanding of clock tree design, DFT, multi-mode multi-corner (MMMC) analysis • Good scripting skills (TCL/Perl/Python) to automate and debug flows • Experience with advanced nodes (7nm/5nm/Fin FET) is a plus • Strong analytical, problem-solving, and communication skills Why Join Wafer Space?• Be part of a high-growth, innovation-driven semiconductor company • Work on state-of-the-art technologies with leading global clients • Collaborative and empowering work culture • Competitive compensation and flexible work options • Opportunity to grow your career in a technically challenging environment Interested? Send your resume to
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Senior/Lead STA engineer
1 week ago
Bangalore, India ACL Digital Full timeWe’re Hiring: STA Engineer | 5–10 Years Experience | Bangalore & Hyderabad Company: ACL Digital Company Location: Bangalore & Hyderabad Experience: 5 to 15 Years Job Type: Full-Time ACL Digital is looking for Senior Static Timing Analysis (STA) Engineers with solid experience in timing closure of advanced SoC designs. If...
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Senior/Lead STA engineer
1 week ago
bangalore, India ACL Digital Full timeWe’re Hiring: STA Engineer | 5–10 Years Experience | Bangalore & HyderabadCompany: ACL Digital CompanyLocation: Bangalore & HyderabadExperience: 5 to 15 YearsJob Type: Full-TimeACL Digital is looking for Senior Static Timing Analysis (STA) Engineers with solid experience in timing closure of advanced SoC designs.If you’re an STA expert who thrives in...
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Senior/Lead STA engineer
1 day ago
bangalore district, India ACL Digital Full timeWe’re Hiring: STA Engineer | 5–10 Years Experience | Bangalore & Hyderabad Company: ACL Digital Company Location: Bangalore & Hyderabad Experience: 5 to 15 Years Job Type: Full-Time ACL Digital is looking for Senior Static Timing Analysis (STA) Engineers with solid experience in timing closure of advanced SoC designs. If you’re an STA...
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Sta engineer
5 days ago
Bangalore, India ACL Digital Full timeJob Title: STA Engineer Location: Banglaore/Hyderabad Employment Type: Full-time Industry: Semiconductors / VLSI / ASIC Design Job Summary: We are looking for a skilled and motivated STA Engineer to join our backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex So C blocks or full-chip designs,...
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STA Engineer
1 day ago
bangalore district, India ACL Digital Full timeJob Title: STA Engineer Location: Banglaore/Hyderabad Employment Type: Full-time Industry: Semiconductors / VLSI / ASIC Design Job Summary: We are looking for a skilled and motivated STA Engineer to join our backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks or full-chip designs,...
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Lead sta engineer
1 day ago
Bangalore, India Tessolve Full timeAbout Us: Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, and spec to the product. With 3200+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing...
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Lead STA Engineer
5 days ago
bangalore, India Tessolve Full timeAbout Us:Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, and spec to the product. With 3200+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing...
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Lead STA Engineer
4 days ago
Bangalore, India Tessolve Full timeAbout Us: Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, and spec to the product. With 3200+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing...
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Senior/staff sta engineer
5 days ago
Bangalore, India Tenstorrent Full timeTenstorrent is looking for a skilled and detail-oriented Static Timing Analysis (STA) Engineer to help us deliver first-pass silicon success for our cutting-edge AI and RISC-V So Cs. Engineers with a strong foundation in Static Timing Analysis (STA) and timing constraints. In this role, you’ll lead timing closure efforts across block and full-chip...
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Senior/Staff STA Engineer
4 days ago
Bangalore, India Tenstorrent Full timeTenstorrent is looking for a skilled and detail-oriented Static Timing Analysis (STA) Engineer to help us deliver first-pass silicon success for our cutting-edge AI and RISC-V SoCs. Engineers with a strong foundation in Static Timing Analysis (STA) and timing constraints . In this role, you’ll lead timing closure efforts across block and full-chip...
