STA Lead

Skills Required Netlist and constraint sign in checks and validation. Prime time constraint development at full chip level and clean up. Multimode multi corner timing knowledge and timing closure at sub HM/block/top level. Top level timing closure with sign off STA in MMMC with Xtalk and OCV. Top level ECO implementation strategy development for...

We’re Hiring: STA Engineer | 5–10 Years Experience | Bangalore & Hyderabad Company: ACL Digital Company Location: Bangalore & Hyderabad Experience: 5 to 15 Years Job Type: Full-Time ACL Digital is looking for Senior Static Timing Analysis (STA) Engineers with solid experience in timing closure of advanced SoC designs. If...

We’re Hiring: STA Engineer | 5–10 Years Experience | Bangalore & HyderabadCompany: ACL Digital CompanyLocation: Bangalore & HyderabadExperience: 5 to 15 YearsJob Type: Full-TimeACL Digital is looking for Senior Static Timing Analysis (STA) Engineers with solid experience in timing closure of advanced SoC designs.If you’re an STA expert who thrives in...

Technical Skills:Well versed with the timing closure (STA), timing closure methodologies.Pre/Post-layout constraint development to timing closure.Handshake with the design team and develop functional/DFT constraints.IP level constraint integration.Multi-voltage/Switching aware corner definitions.RC/C model selection understanding.Abstraction expertise like...

BE /Btech EXp- 5- 12 Yrs Work on challenging DDR PHY IP & Testchip Physical Design from Netlist-to-GDS in tech nodes below 7nm. • Take ownership of one or more physical design blocks includes all of, floorplan, CTS, PNR, QRC, STA, PV & IR. • Contribute to design methodology, flow automation. • Innovate & implement Power, Performance and Area...

Role Proficiency Execute any sized customer projects independently with minimum supervision Guide team members technically in any field of VLSI Frontend Backend or Analog designOutcomes As an Individual contributor take ownership for any one or more task module of RTL Design Module Verification PD DFT Circuit Design Analog Layout STA Synthesis Design...

Hello Folks, we at LTTS are looking for Physical design Lead role with 8+ years of experience. Deatiled JD is below as mentioned...Candidates with PnR – 8+ ’ experience • IP/Block level PnR activities from Netlist to GDS-II. • Good knowledge of all PnR activities like Floor-planning, Placement, CTS, Routing, Timing closure(STA), signoff checks like...

LTTS is hiring for Physical Design Lead with 7+ years of experience on below JD ::JD for PnR – 7+ ’ experience • IP/Block level PnR activities from Netlist to GDS-II. • Good knowledge of all PnR activities like Floor-planning, Placement, CTS, Routing, Timing closure(STA), signoff checks like FEV, VCLP, EMIR and PV. • Knowledge of industry stanrd E...

Job Description: We are seeking a Physical Design Lead with strong expertise in RTL-to-GDSII flow for advanced technology nodes (7nm and below). The role involves leading SoC/IP physical implementation, driving PPA goals, and ensuring successful tapeouts. You will manage a team, interface with cross-functional groups, and own block/top-level execution....

Role: PD Lead Experience: 7+yrs Location: Bangalore Technical Skills: Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks and signoff DRC/LVS closure ...