Lead Sta

Full Chip STA Lead (8+ Years Experience) Locations: Bangalore, Hyderabad, Noida, Ahmedabad, Chennai, Pune Job Description: We are looking for an experienced Full Chip STA Lead with strong expertise in full-chip timing, constraint management, and cross-functional collaboration. The ideal candidate will drive timing closure activities for complex SoCs and...

Full Chip STA Lead (8+ Years Experience)Locations: Bangalore, Hyderabad, Noida, Ahmedabad, Chennai, PuneJob Description: We are looking for an experienced Full Chip STA Lead with strong expertise in full-chip timing, constraint management, and cross-functional collaboration. The ideal candidate will drive timing closure activities for complex SoCs and...

Technical Skills:Well versed with the timing closure (STA), timing closure methodologies.Pre/Post-layout constraint development to timing closure.Handshake with the design team and develop functional/DFT constraints.IP level constraint integration.Multi-voltage/Switching aware corner definitions.RC/C model selection understanding.Abstraction expertise like...

Technical Skills: Well versed with the timing closure (STA), timing closure methodologies. Pre/Post-layout constraint development to timing closure. Handshake with the design team and develop functional/DFT constraints. IP level constraint integration. Multi-voltage/Switching aware corner definitions. RC/C model selection understanding. Abstraction expertise...

Location- Bangalore/ Noida/ Hyderabad 4+ years experience in STA/Synthesis Hand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis. Synthesis Quality with FE Inputs, LEC environment, UPF Cleanup, Generic Partition level UPF ? and VCLP Signoff. USER mode SDC (will have generic dft constraints), Generic DFT SDC, GCA, Flat Timing...

Location- Bangalore/ Noida/ Hyderabad 4+ years experience in STA/Synthesis Hand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis. Synthesis Quality with FE Inputs, LEC environment, UPF Cleanup, Generic Partition level UPF ? and VCLP Signoff. USER mode SDC (will have generic dft constraints), Generic DFT SDC, GCA, Flat Timing...

BE /BtechEXp- 5- 12 YrsWork on challenging DDR PHY IP & Testchip Physical Design from Netlist-to-GDS in tech nodes below 7nm.• Take ownership of one or more physical design blocks includes all of, floorplan, CTS, PNR, QRC, STA, PV & IR.• Contribute to design methodology, flow automation.• Innovate & implement Power, Performance and Area optimization...

BE /Btech EXp- 5- 12 Yrs Work on challenging DDR PHY IP & Testchip Physical Design from Netlist-to-GDS in tech nodes below 7nm. • Take ownership of one or more physical design blocks includes all of, floorplan, CTS, PNR, QRC, STA, PV & IR. • Contribute to design methodology, flow automation. • Innovate & implement Power, Performance and Area...

• SoC/Blocks Synthesis/STA methodology & flow for meeting PPA goals• Work with Backend team in realizing PPA goals during PnR & IP & SoC Design team in optimizing the design to meet PPA goals.• Feedback on design issues & solutions. Required Candidate profile• Exp in front end design implementation.• Design flows like Synthesis, Constraint Devel.,...

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today s needs and tomorrow s next big ideas With a rich history of groundbreaking innovations in Flash and advanced memory technologies our solutions have become the beating heart of the digital world we re living in...