Lead STA

Skills Required Netlist and constraint sign in checks and validation. Prime time constraint development at full chip level and clean up. Multimode multi corner timing knowledge and timing closure at sub HM/block/top level. Top level timing closure with sign off STA in MMMC with Xtalk and OCV. Top level ECO implementation strategy development for...

We’re Hiring: STA Engineer | 5–10 Years Experience | Bangalore & Hyderabad Company: ACL Digital Company Location: Bangalore & Hyderabad Experience: 5 to 15 Years Job Type: Full-Time ACL Digital is looking for Senior Static Timing Analysis (STA) Engineers with solid experience in timing closure of advanced SoC designs. If...

Technical Skills: Well versed with the timing closure (STA), timing closure methodologies. Pre/Post-layout constraint development to timing closure. Handshake with the design team and develop functional/DFT constraints. IP level constraint integration. Multi-voltage/Switching aware corner definitions. RC/C model selection understanding. ...

Job Description: We are seeking a Physical Design Lead with strong expertise in RTL-to-GDSII flow for advanced technology nodes (7nm and below). The role involves leading SoC/IP physical implementation, driving PPA goals, and ensuring successful tapeouts. You will manage a team, interface with cross-functional groups, and own block/top-level execution....

Role: PD Lead Experience: 7+yrs Location: Bangalore Technical Skills: Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks and signoff DRC/LVS closure ...

Role: PD Lead Experience: 7+yrs Location: Bangalore Technical Skills: Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks and signoff DRC/LVS closure...

Role Overview: Job Title : PNR Lead Experience : 8+ Years Work location : Bangalore Job Description: Technical Skills: Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep understanding of the concepts related to synthesis, place & route, CTS, timing...

Role: PD LeadExperience: 7+yrsLocation: BangaloreTechnical Skills: Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks and signoff DRC/LVS closure Responsible for...

Job Description- The candidate is expected to have clear understanding of IJTAG, P1500 protocols and should have hands on experience of at least one of these. The candidate is expected to have clear understanding of BSCAN,MBIST, SCAN, ATPG and Simulation concepts. Must be hands-on with MBIST insertion, Scan Insertion, ATPG pattern generation and...

ob Title: Senior Design Verification Engineer – IP/SoC/Processor/GLS Experience: 5 to 15 Years Location: (Insert Location – e.g., Bangalore / Hyderabad / Chennai / Noida ) Company: Tessolve Semiconductor Job Type: Full-Time | Permanent Domain: Semiconductor – Design Verification Job Summary: Tessolve is hiring experienced ...