Senior/Lead STA engineer
1 day ago
We’re Hiring: STA Engineer | 5–15 Years Experience | Bangalore Company: ACL Digital Company Location: Bangalore Experience: 5 to 15 Years Job Type: Full-Time ACL Digital is looking for Senior Static Timing Analysis (STA) Engineers with solid experience in timing closure of advanced SoC designs. If you’re an STA expert who thrives in fast-paced, technically challenging environments, we want to hear from you Responsibilities: • Own and drive timing closure for complex SoC and ASIC designs across multiple technology nodes • Perform full-chip and block-level timing analysis using industry-standard tools (Primetime, Tempus, etc.) • Collaborate with RTL, synthesis, physical design, and verification teams to resolve timing violations • Develop and maintain timing constraints (SDC), run STA checks (setup, hold, DRV, SI), and support ECO timing closure • Contribute to methodology improvements and timing signoff strategies • Report timing status, risks, and closure plans to technical leads and project stakeholders Required Skills & Experience: • 5–15 years of solid hands-on experience in STA and timing closure • Strong expertise in timing concepts, constraints development, and signoff methodology • Proficient in tools like Synopsys Primetime, Cadence Tempus • Solid understanding of clock tree design, DFT, multi-mode multi-corner (MMMC) analysis • Good scripting skills (TCL/Perl/Python) to automate and debug flows • Experience with advanced nodes (7nm/5nm/FinFET) is a plus • Strong analytical, problem-solving, and communication skills Why Join Wafer Space? • Be part of a high-growth, innovation-driven semiconductor company • Work on state-of-the-art technologies with leading global clients • Collaborative and empowering work culture • Competitive compensation and flexible work options • Opportunity to grow your career in a technically challenging environment Interested? Send your resume to
-
Senior/Lead STA engineer
17 hours ago
bangalore, India ACL Digital Full timeWe’re Hiring: STA Engineer | 5–15 Years Experience | BangaloreCompany: ACL Digital CompanyLocation: BangaloreExperience: 5 to 15 YearsJob Type: Full-TimeACL Digital is looking for Senior Static Timing Analysis (STA) Engineers with solid experience in timing closure of advanced SoC designs.If you’re an STA expert who thrives in fast-paced, technically...
-
Senior/Lead STA engineer
3 weeks ago
Bangalore Division, India ACL Digital Full timeWe’re Hiring: STA Engineer | 5–15 Years Experience | Bangalore Company: ACL Digital Company Location: Bangalore Experience: 5 to 15 Years Job Type: Full-Time ACL Digital is looking for Senior Static Timing Analysis (STA) Engineers with solid experience in timing closure of advanced SoC designs. If you’re an STA expert who thrives in fast-paced,...
-
Senior STA Engineer
4 days ago
bangalore, India NXP Semiconductors Full timeSummary: The Digital Physical Design Engineer is responsible for a physical implementation of IP, Subsystem or IC design.Job qualification:Experience range: 4-7 yearsShould be good in Synthesis Flow setup and Synthesis flows. Should have worked on Genus flows.Should be good in STA flow setup and STA flows. Should have worked in Tempus flows. Should have...
-
STA Engineer
1 day ago
Bangalore, India ACL Digital Full timeJob Title: STA Engineer Location: Banglaore/Hyderabad Employment Type: Full-time Industry: Semiconductors / VLSI / ASIC Design Job Summary: We are looking for a skilled and motivated STA Engineer to join our backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, targeting...
-
STA Engineer
2 days ago
bangalore, India ACL Digital Full timeJob Title: STA EngineerLocation: Banglaore/HyderabadEmployment Type: Full-timeIndustry: Semiconductors / VLSI / ASIC DesignJob Summary:We are looking for a skilled and motivated STA Engineer to join our backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, targeting...
-
Senior Sta Engineer
3 days ago
Bangalore, Karnataka, India Qualcomm Full timeCompany Qualcomm India Private Limited Job Area Engineering Group Engineering Group Hardware Engineering General Summary As a leading technology innovator Qualcomm pushes the boundaries of what s possible to enable next-generation experiences and drives digital transformation to help create a smarter connected future for all As a Qualcomm Hardware Engineer...
-
STA Engineer
3 weeks ago
Bangalore Division, India ACL Digital Full timeJob Title: STA Engineer Location: Banglaore/Hyderabad Employment Type: Full-time Industry: Semiconductors / VLSI / ASIC Design Job Summary: We are looking for a skilled and motivated STA Engineer to join our backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, targeting...
-
STA Engineer
18 hours ago
bangalore district, India ACL Digital Full timeJob Title: STA Engineer Location: Banglaore/Hyderabad Employment Type: Full-time Industry: Semiconductors / VLSI / ASIC Design Job Summary: We are looking for a skilled and motivated STA Engineer to join our backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, targeting...
-
Full Chip STA Lead
15 hours ago
bangalore, India eInfochips (An Arrow Company) Full timeFull Chip STA Lead (8+ Years Experience)Locations: Bangalore, Hyderabad, Noida, Ahmedabad, Chennai, PuneJob Description: We are looking for an experienced Full Chip STA Lead with strong expertise in full-chip timing, constraint management, and cross-functional collaboration. The ideal candidate will drive timing closure activities for complex SoCs and...
-
STA Engineers
3 days ago
Bangalore, India LeadSoc Technologies Pvt Ltd Full timeStatic Timing Analysis (STA) Engineer Job Summary The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with design and...