STA Engineers
7 hours ago
Static Timing Analysis (STA) Engineer Job Summary The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with design and physical design teams to achieve the target operating frequency and performance metrics. Key Responsibilities Timing Sign-off and Analysis Timing Closure Ownership: Drive all aspects of timing closure from pre-layout to post-layout for blocks, sub-systems, and/or the full chip. Constraint Management: Develop, validate, and maintain Synopsys Design Constraints (SDC) and timing constraints for all functional and test modes (e.g., Scan, MBIST). MMMC Analysis: Perform comprehensive timing analysis across multiple operating corners (Process, Voltage, Temperature - PVT) and various modes (Multi-Mode Multi-Corner). Critical Path Identification: Analyze timing reports to identify and debug critical paths and resolve all Setup and Hold violations. Signal Integrity (SI) & Noise: Incorporate advanced timing effects such as on-chip variation (OCV), signal integrity (crosstalk), and voltage drop (IR-drop aware STA) into the sign-off process. Methodology and Flow Develop, maintain, and enhance STA flows and methodologies to improve efficiency, robustness, and reduce analysis runtime. Automate repetitive tasks and report generation using scripting languages. Generate final timing reports and sign-off collateral for tape-out. Education Bachelor's or Master's degree in Electrical Engineering (EE), Electronics Engineering, VLSI, or a related field. Technical Skills & Experience Experience: 3+ years of experience in STA. EDA Tools: Expert proficiency with industry-standard Electronic Design Automation (EDA) tools from vendors like Synopsys (e.g., Fusion Compiler, ICC2, Primetime), Cadence (e.g., Innovus), or Mentor Graphics. Soft Skills Excellent analytical, debugging, and problem-solving skills. Strong verbal and written communication skills. Ability to work effectively in a team environment and collaborate across different engineering disciplines. Experience Level :- 3yrs to 15yrs Notice Period :- Immediate to 60 Days Work Location :- Bangalore Mode of Work :- WFO Employment Type :- Permanent
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STA Engineer
2 weeks ago
Bangalore Division, India ACL Digital Full timeJob Title: STA Engineer Location: Banglaore/Hyderabad Employment Type: Full-time Industry: Semiconductors / VLSI / ASIC Design Job Summary: We are looking for a skilled and motivated STA Engineer to join our backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, targeting...
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STA Engineer
1 week ago
Bangalore, India ACL Digital Full timeRole: STA Engineer Experience: 3+ Years Location: Bangalore (Onsite) Notice Period: Immediate to 30 Days / Serving Notice Key Responsibilities: Perform Static Timing Analysis (STA) at block and full-chip levels across multiple design stages (synthesis, P&R, sign-off). Develop, validate, and maintain timing constraints (SDC files) for complex SoC and IP-level...
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STA Engineers
3 days ago
bangalore, India LeadSoc Technologies Pvt Ltd Full timeStatic Timing Analysis (STA) EngineerJob Summary The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with design and...
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STA CAD Engineer
4 days ago
Bangalore, India ACL Digital Full timeGreetings from ACL Digital We are looking for STA CAD Engineers. Experience Level:4+ years of STA CAD Job Description: STA CAD Engineer Location: Hyderabad and Bangalore Job Description: Bachelor's degree in Electrical or Computer Engineering and 4+ years STA (Timing, Constrains)/CAD experience or Master's degree and 2+ years' experience • Excellent...
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Senior STA Engineer
1 day ago
bangalore, India NXP Semiconductors Full timeSummary: The Digital Physical Design Engineer is responsible for a physical implementation of IP, Subsystem or IC design.Job qualification:Experience range: 4-7 yearsShould be good in Synthesis Flow setup and Synthesis flows. Should have worked on Genus flows.Should be good in STA flow setup and STA flows. Should have worked in Tempus flows. Should have...
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STA Engineers
7 days ago
Bangalore Division, India LeadSoc Technologies Pvt Ltd Full timeStatic Timing Analysis (STA) Engineer Job Summary The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with design and...
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STA Engineer
2 weeks ago
bangalore, India Mirafra Technologies Full timeJob Description:STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.Evaluate multiple timing methodologies/tools on different designs and technology...
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STA CAD Engineer
2 weeks ago
bangalore, India ACL Digital Full timeGreetings from ACL DigitalWe are looking for STA CAD Engineers.Experience Level:4+ years of STA CADJob Description: STA CAD EngineerLocation: Hyderabad and BangaloreJob Description:Bachelor's degree in Electrical or Computer Engineering and 4+ years STA (Timing, Constrains)/CAD experience or Master's degree and 2+ years' experience • Excellent...
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STA Engineer
2 days ago
bangalore, India ACL Digital Full timeRole: STA EngineerExperience: 3+ YearsLocation: Bangalore (Onsite)Notice Period: Immediate to 30 Days / Serving NoticeKey Responsibilities:Perform Static Timing Analysis (STA) at block and full-chip levels across multiple design stages (synthesis, P&R, sign-off).Develop, validate, and maintain timing constraints (SDC files) for complex SoC and IP-level...
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STA Engineer
5 days ago
bangalore, India Mirafra Technologies Full timeExp 5-8Yrs relevantLocation- GermanyDeliverables and Results: Timing and power Signoff dataDigital timing and power sign-off guidelinesReports, analysis and scripts (perl/python) to improve MethodologyRequirements:A sound knowledge in digital chip design including timing, power and IR drop analysis and verification as well as functional simulationDeep...
