ASIC/SOC Front End Design Engineer

1 week ago


Hyderabad, Telangana, India Proxelera Full time ₹ 15,00,000 - ₹ 25,00,000 per year
Job Information

Job Opening ID

ZR_186_JOB

Industry

Semiconductor

Date Opened

09/18/2025

Job Type

Full time

Work Experience

3 - 10 years

City

Hyderabad

State/Province

Telangana

Country

India

Zip/Postal Code

5600081

Job Description

Role: ASIC/SOC Front End Design Engineer

Experience: 3–10+ years of relevant experience.

Location: Hyderabad

Design Openings – 2 Positions

Screen the profiles with relevant experience before sharing; your support is highly appreciated.

Job Description:

  • Setup ASIC QA flows for RTL design quality checks.
  • Understand the design: top-level interfaces, clock structure, reset structure, RAMs, CDC boundaries, power domains.
  • Running Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, CLP steps.
  • Come up with clock constraints, false paths, multi-cycle paths, IO delays, exceptions and waivers.
  • Checking the flow errors, design errors & violations and reviewing the reports.
  • Debugging CDC, RDC issues and come up with the RTL fixes.
  • Supporting DFX team for DFX controller integration, Scan insertion, MBIST insertion and DFT DRC & MBIST checks.
  • Handling multiple PNR blocks, building wrappers and propagating constraints, waivers, etc.
  • Flows or Design porting to different technology libraries.
  • Generating RAMs based on targeted memory compilers and integrating with the RTL.
  • Running functional verification simulations as needed.

Job Requirements:

  • ASIC design flow and direct experience with ASIC design in sub-20nm technology nodes.
  • Modern SOC tools including Spyglass, Synopsys Design Compiler & Primetime, Questa CDC, Cadence Conformal, VCS simulation.
  • Experience in signoff of front-end quality checks & metrics for various milestones of the project.
  • TCL, Perl, Python scripting.
  • B.E/M.E/M.Tech or B.S/M.S in EE/CE with

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