ASIC Design Verification

2 weeks ago

Hyderabad, Telangana, India Cyient Full time

Job Title: ASIC Design Verification (DV) Lead

Company: Cyient Semiconductor

Location: Hyderabad, India

Experience Required: 10 to 20 years

Employment Type: Full-Time / Permanent

About Cyient Semiconductor:

Cyient Semiconductor, a part of Cyient Ltd., is driving innovation across cutting-edge SoC, ASIC, and Mixed-Signal design programs for global customers. Our team combines deep domain expertise with world-class design and verification capabilities to deliver high-performance silicon solutions. Join us to be part of a dynamic organization shaping the next generation of semiconductor technologies.

Role Overview:

We are looking for an experienced ASIC Design Verification Lead to join our growing verification team in Hyderabad. The ideal candidate will have strong hands-on expertise in Verilog, System Verilog (SV), and UVM-based verification, along with experience in testbench development, gate-level simulations, and UPF-based low power verification.

As a DV Lead, you will be responsible for leading a team of verification engineers, defining verification strategy, developing test environments, and ensuring quality deliverables for complex SoC/ASIC projects.

Key Responsibilities:

  • Lead end-to-end ASIC/SoC Verification activities for block-level and full-chip environments.
  • Architect and develop UVM-based testbenches and reusable verification components.
  • Define verification strategy, test plans, and coverage goals to ensure design quality.
  • Drive functional, gate-level, and low-power (UPF) verification closure.
  • Collaborate with design, synthesis, DFT, and validation teams to ensure smooth handoff and debug cycles.
  • Manage verification deliverables, schedules, and task allocation for the team.
  • Mentor junior engineers and provide technical leadership across verification domains.
  • Support regression setup, debug of complex simulation issues, and coverage analysis.

Required Skills and Experience:

  • 10-20 years of strong hands-on experience in ASIC/SoC Design Verification.
  • Excellent knowledge of Verilog, System Verilog, and UVM methodology.
  • Proven experience in Testbench Architecture, Environment Development, and Functional Coverage.
  • Exposure to Gate-Level Simulations (GLS), Low-Power Verification (UPF/CPF), and Power-Aware Simulations.
  • Familiarity with simulation and debugging tools (VCS, Incisive, Questa, Verdi, DVE, etc.).
  • Good understanding of ASIC design flow, synthesis, and timing concepts.
  • Strong analytical and problem-solving skills with an eye for detail.
  • Excellent communication and leadership abilities.

Good to Have:

  • Experience in SoC-level verification or subsystem integration.
  • Exposure to Assertion-Based Verification (ABV) and Formal Verification.
  • Working knowledge of Python/Perl/TCL scripting for automation.

Education:

  • B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, or related field.

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