Staff / Senior Staff ASIC Design Engineer

1 day ago

Hyderabad, Telangana, India Cyient Full time ₹ 8,00,000 - ₹ 20,00,000 per year

Job Title: Staff / Senior Staff ASIC Design Engineer

Company: Cyient Semiconductor

Location: Hyderabad, India

Experience Required: 6 to 10 years

Employment Type: Full-Time / Permanent

About Cyient Semiconductor:

Cyient Semiconductor, a division of Cyient Ltd., enables global semiconductor innovation through comprehensive ASIC, SoC, and Mixed-Signal design services. With expertise across advanced technology nodes and deep partnerships with leading foundries and OEMs, we deliver end-to-end silicon design solutions.

Join a team that values technical excellence, innovation, and collaboration, and work on next-generation SoC/ASIC programs for global semiconductor leaders.

Role Overview:

We are looking for a highly skilled ASIC Design Engineer (Staff / Sr. Staff level) with strong experience in RTL Design, Synthesis, Timing Constraints, and Scripting Automation.

The ideal candidate will be responsible for RTL development and design implementation for complex SoC/ASIC blocks, driving design quality, synthesis readiness, and efficient timing closure.

This is an opportunity to work in a fast-paced environment with exposure to latest technology nodes and high-performance designs.

Key Responsibilities:

  • Perform RTL coding and integration for complex SoC/ASIC blocks using Verilog or System Verilog.
  • Develop micro-architecture specifications, interface documents, and design documentation.
  • Own the complete RTL design flow from specification to synthesis handoff.
  • Perform RTL linting, CDC, RDC, and design quality checks.
  • Collaborate closely with verification, synthesis, physical design, and DFT teams to ensure high-quality design signoff.
  • Develop and maintain timing constraints (SDC) for block and top-level synthesis.
  • Drive synthesis, timing analysis, and constraint validation to achieve optimal PPA (Performance, Power, Area).
  • Create and enhance scripts (TCL/Perl/Python) to automate design and synthesis workflows.
  • Contribute to design reviews, root-cause analysis, and design closure activities.
  • Mentor junior engineers in design practices, coding standards, and tool usage.

Required Skills and Experience:

  • 610 years of hands-on experience in ASIC / SoC RTL Design.
  • Strong proficiency in Verilog / SystemVerilog RTL coding.
  • Excellent understanding of synthesis flow, timing closure, and constraint development (SDC).
  • Hands-on experience with EDA tools such as Synopsys Design Compiler, Fusion Compiler, or Cadence Genus.
  • Knowledge of static timing analysis (STA) concepts and design optimization.
  • Experience in developing and validating design constraints.
  • Proficiency in scripting languages (TCL, Perl, Python, Shell) for automation.
  • Strong understanding of SoC architecture, clock/reset domains, and power management techniques.
  • Good analytical and problem-solving skills with attention to design quality.
  • Excellent communication and teamwork skills.

Good to Have:

  • Exposure to DFT insertion, floorplanning constraints, or timing ECO flows.
  • Knowledge of low power design techniques (UPF/CPF).
  • Familiarity with lint/CDC tools (SpyGlass, VC-Lint, Questa CDC, etc.).
  • Experience in high-performance or low-power ASICs at advanced nodes (e.g., 7nm, 5nm).

Education:

  • B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, or VLSI Design Engineering.

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