Staff FPGA/Soc Integration Engineer

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Job Description:

The staff FPGA/SoC integration engineer will be responsible for integrating all custom and external IP's into the FPGA top. This high visibility role involves ownership of chip top RTL, place/route and timing closure and other deliverables needed to release the FPGA for production.

Duties & Responsibilities

• Develop flows and methodologies that improves on current methodology  to integrate complex IP's into FPGA chip-top using digital-on-top (DoT) approach.
• Develop tools and scripts (RTL and custom scripts) to verify connectivity and functionality of chip-top.
• Own chip level floorplan activities, place and route, timing closure, and physical and electrical verification.
• Coordinate activities between different groups like architecture, design, software and verification to ensure smooth integration of various IP's into the chip top.
• Generate netlists with different views for software, physical, electrical and functional verification.
• Collaborate with the packaging team to generate package files for several different members of the FPGA product family.
• Work with verification team to help debug chip top level integration issues related to timing and functionality.
• Effectively presenting technical information to small teams of engineers.
• Communicate regularly with the management, design and verification teams in multiple locations to resolve issues, update status and solve technical problems related to chip/SoC integration and delivery.
• Become well-versed in new ASIC and custom tools related to chip integration.

Requirements/Qualifications:

​Experience Required

• Minimum of 15years  of proven silicon design experience in ASIC design flow including RTL design, implementation, functional validation.
• Extensive knowledge of integration of several complex custom and ASIC IP's at chip-top level using DoT(digital on top) methodology.
• Expert in ASIC flow and methodology.
• Experience with System Verilog/Verilog, synthesis, STA and place and route is required.
• Expert in usage of  ASIC tools like Innovus, Tempus, Magillem, Verdi or similar is required.

Other Requirements

• Demonstrated competency in scripting, managing simulation queues, and data capture plus presentation using Microsoft Office tools, including Excel.
• Ability to support layout, verification, timing characterization, and software model developers.
• Good analytical, oral and written communication skills
• Able to write clean, readable presentations.
• Self-motivated, proactive team player.
• Ability to work to schedule requirements.

Beneficial Experience

• Experience in ASIC development, several technology nodes.
• Experience with verification methodologies such as SystemVerilog/UVM.
• Experience in low power design.

Qualification:

Bachelors or Master's in Electrical Engineering, Physics, Computer Engineering or Computer Science preferred.

Travel Time:

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