ASIC/SOC Front End DV
2 days ago
Job Opening ID
ZR_187_JOB
Industry
Semiconductor
Date Opened
09/18/2025
Job Type
Full time
Work Experience
3 - 10 years
City
Hyderabad
State/Province
Telangana
Country
India
Zip/Postal Code
5600081
Job DescriptionRole: ASIC/SOC Front End DV (Design Verification) Engineer
Experience:3–10+ years of relevant experience.
Location: Hyderabad
Job Description:
- A major part of your responsibility will be to take an independent verification role in developing TB architecture definition and TB infrastructure/test coding development for PCIe/Networking/IP Sub-Systems.
- Understanding product specifications and deriving the TB architectures.
- Developing verification plan, test plan, coverage plan, assertions, etc.
- Developing block-level and multi block-level verification environments & reusable verification components based on SV/UVM methodology.
- Coverage metrics to ensure conformity, running regressions, debug test failures, and regression management.
- Knowledge and working experience with any of the complex protocols like PCIe/Ethernet/DMAs/Cryptography/Others – an advantage.
- Experience in scripting languages like Perl or Python.
- Knowledge in AMBA AXI, APB, etc. – an advantage.
- Ability to work collaboratively with other team members and have good ownership and accountability.
- Assisting validation teams with on board-level test issues, educating design teams on verification methodology.
- Contributing to process improvement in verification methodologies that impact productivity.
- Strong oral and written communication skills, problem-solving and analytical skills.
Job Requirements:
- Working experience with latest SOC tools including Questa, Cadence Conformal, VCS simulation.
- B.E/M.E/M.Tech or B.S/M.S in EE/CE
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