ASIC Engineer, RTL Integration

5 days ago

Bengaluru, Karnataka, India Google Full time ₹ 15,00,000 - ₹ 25,00,000 per year
Minimum qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 3 years of experience with Register-Transfer Level (RTL) design and integration using Verilog/System Verilog, microarchitecture and automation.
  • 3 years of experience with the Register-Transfer Level quality check tool flows (e.g., Lint, Clock Domain Crossing, Reset Domain Crossing, Synthesis).
Preferred qualifications:
  • Experience with methodologies for Register-Transfer Level (RTL) quality checks (e.g., Lint, CDC, RDC).
  • Experience with IP integration methodology, IP Design, ARM-based SoCs, ARM-protocols and ASIC methodology.
  • Experience with methodologies for low power estimation, timing closure, synthesis.
  • Knowledge in one or more of these areas: Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin Multiplexing.
About the job:

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities:
  • Define microarchitecture details for integration of Intellectual Property's (IPs) at macro/Sub-System Workload Requirements Plan (SSWRP) level.
  • Perform RTL development (SystemVerilog), debug functional/performance simulations.
  • Perform RTL quality checks including Lint, Clock Domain Crossing (CDC), Synthesis, Unified Power Format (UPF) checks.
  • Participate in synthesis, timing/power estimation and FPGA/silicon bring-up.

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