RTL Design Engineer

18 minutes ago

Bengaluru, Karnataka, India Sauvira Solutions Private Limited Full time ₹ 12,00,000 - ₹ 36,00,000 per year

The ASIC RTL Design Lead Engineer will lead the design and development of RTL for high-performance, low-power ASICs. The candidate will be responsible for architecting, designing, and implementing digital circuits using industry-standard RTL design methodologies. This individual will also manage a team of design engineers, provide technical leadership, and work closely with cross-functional teams such as verification, physical design, and software teams.

Key Responsibilities
:

  • Lead and manage RTL design activities for complex ASICs, ensuring high performance and low power consumption.
  • Integrating RTL components into System-on-Chip (SoC) designs Integrating RTL components into System-on-Chip (SoC) designs
  • Architect and implement RTL for digital circuits (such as processors, communication systems, or custom IP cores).
  • Mentor and guide junior RTL engineers in best practices for design, coding standards, and optimization techniques.
  • Develop and refine RTL code in Verilog/System Verilog for ASIC development.
  • Collaborate with cross-functional teams (Verification, Physical Design, and Software) to ensure successful integration of the ASIC design.
  • Perform RTL design reviews, debugging, and optimization to meet design targets such as area, speed, and power.
  • Work on creating micro-architectural specifications and ensure the design meets project requirements.
  • Ensure designs are implemented with proper synchronization, timing constraints, and low power techniques.
  • Participate in top-level design, integrating IP blocks, ensuring design consistency across subsystems.
  • Drive the design flow from architecture and specifications through to implementation.
  • Prepare and maintain technical documentation for designs and related processes.
  • CDC, LINT and Integration expertise is expected.

Required Skills & Experience
:

  • Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or related fields.
  • 3-12 years of experience in RTL design for ASICs, with at least 3 years in a team lead role.
  • Expertise in RTL design using Verilog or System Verilog.
  • Solid understanding of digital design principles, including timing analysis, state machines, and pipelining.
  • In-depth knowledge of ASIC design flow, from RTL to tape-out.
  • Experience with EDA tools for synthesis, simulation, and timing analysis (e.g., Synopsys, Cadence).
  • Strong debugging and problem-solving skills.
  • Good knowledge on scripting (Python, Perl and Shell scripting)
  • Knowledge of power, performance, and area (PPA) optimization techniques.
  • Experience with designing for low-power, high-speed circuits is highly desirable.
  • Excellent communication skills and the ability to work in a team environment.

Preferred Skills
:

  • Experience with complex subsystems such as memory controllers, interconnects, or high-speed I/O.
  • Prior experience working with large, cross-functional teams and managing design schedules.
  • Experience with software tools for RTL analysis and optimization.

Hands-on experience in leading ASIC projects from specification to production

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