RTL Logic Design

2 days ago

Bengaluru, Karnataka, India Vyeco Solutions LLP Full time ₹ 12,00,000 - ₹ 36,00,000 per year

Job Title: Senior Design Verification Engineer

Location: Bengaluru

Experience: 7+ years

Responsibilities:


• Work with design and architecture teams to create test plans for configurable IPs used in SOC or multi-chip systems.


• Develop UVM/SystemVerilog-based testbenches, checkers, and scoreboards.


• Collaborate with software and DV teams to implement and debug test environments.


• Analyze and resolve verification failures and drive coverage closure. Qualifications:


• 6+ years of hands-on experience in IP/SOC-level verification.


• Strong skills in Verilog, SystemVerilog, and UVM methodology.


• Experience with EDA simulation and debug tools.


• Working knowledge of Python or similar scripting languages.


• Familiarity with ARM AMBA protocols (AXI, APB, AHB); CHI protocol experience is a plus.


• Exposure to cache, memory subsystem, interconnect, or NoC IPs.


• Experience with formal verification or emulation platforms is a plus.

RTL Logic Design Engineer — Job Description

Location BLR/ SG

Exp: 8+

Primary Responsibilities:


• Ensure high quality deliverables from RTL (Register Transfer Level) through to Physical Design.


• Learn, customize, and maintain synthesis flow; set up synthesis environment and perform synthesis ensuring high quality of results.


• Create, analyze, and maintain timing constraints / SDCs (Synopsys Design Constraints or similar).


• Analyze and drive UPF (Unified Power Format) solutions for low power design checks and compliance.


• Drive RTL-to-synthesis flow, ensuring the design is clean for FEV (Formal Equivalence Verification).


• Collaborate between RTL (front-end) and Physical Design (back-end) teams to incorporate design feedback and maintain/enhance design quality. Additional / Related Responsibilities


• Implement micro-architectural specifications in Verilog or SystemVerilog.


• Contribute to unit, subsystem, and SoC-level architecture.


• Integrate functional block RTLs into a full SoC RTL.


• Perform design quality checks: Lint, CDC, Reset Domain Crossing (RDC), synthesis warnings, low power intent, etc.


• Work with verification teams to ensure functional correctness and meet architectural / micro-architectural intent.


• Interfacing / working with Physical Design (PD), Design for Test (DFT), verification, performance modelling, power/performance/area trade-offs.


• Writing basic tests, debugging at IP / SoC levels. Some scripting or automation may be involved.

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