Senior RTL Design Engineer DSP/ASIC/FPGA
1 day ago
Senior RTL Design Engineer DSP / ASIC / FPGA
Experience: 10 to 15 years
Location: Bangalore (On-site)
Employment Type: Full-time / Permanent
About the Role
We are seeking a highly skilled Senior RTL Design Engineer to join our digital design team. The selected candidate will be responsible for the RTL design and development of signal processing pipelines for high-performance ASIC and FPGA-based SoCs.
Key Responsibilities
- Develop and integrate custom sub-components of the digital signal processing pipeline such as filters, FFTs, control logic, etc.
- Write micro-architecture specifications, code RTL, and perform verification and validation of DSP components.
- Optimize RTL for performance, area, and power.
- Work closely with system architects, verification, and software teams to meet functionality and performance targets.
- Support FPGA prototyping and post-silicon validation efforts.
Required Skills
- 10+ years of experience in DSP/RTL design for ASICs and FPGAs.
- Strong expertise in Verilog / SystemVerilog RTL coding and AMBA protocols (AXI, AHB, APB).
- Experience implementing DSP algorithms (FFT, FIR, IIR, filtering, modulation).
- Hands-on experience in FPGA synthesis, simulation, and timing closure.
- Familiarity with EDA tools (Synopsys DC, Cadence Genus, Xilinx Vivado, QuestaSim).
- Proven ability to achieve high-performance and low-power targets.
Good to Have
- Experience with Matlab / NumPy / C / C++ for DSP modeling.
- Exposure to LPDDR, Ethernet, MIPI, or SerDes interfaces.
- Experience in FPGA prototyping or emulation (Palladium, Veloce, Zebu).
- Knowledge of functional safety (ISO and post-silicon bring-up.
Education
- B.E / B.Tech / M.Tech in Electronics or related discipline.
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