Senior RTL Design Engineer DSP/ASIC/FPGA
3 days ago
Senior RTL Design Engineer DSP / ASIC / FPGA
Experience: 10 to 15 years
Location: Bangalore (On-site)
Employment Type: Full-time / Permanent
About the Role
We are seeking a highly skilled Senior RTL Design Engineer to join our digital design team. The selected candidate will be responsible for the RTL design and development of signal processing pipelines for high-performance ASIC and FPGA-based SoCs.
Key Responsibilities
- Develop and integrate custom sub-components of the digital signal processing pipeline such as filters, FFTs, control logic, etc.
- Write micro-architecture specifications, code RTL, and perform verification and validation of DSP components.
- Optimize RTL for performance, area, and power.
- Work closely with system architects, verification, and software teams to meet functionality and performance targets.
- Support FPGA prototyping and post-silicon validation efforts.
Required Skills
- 10+ years of experience in DSP/RTL design for ASICs and FPGAs.
- Strong expertise in Verilog / SystemVerilog RTL coding and AMBA protocols (AXI, AHB, APB).
- Experience implementing DSP algorithms (FFT, FIR, IIR, filtering, modulation).
- Hands-on experience in FPGA synthesis, simulation, and timing closure.
- Familiarity with EDA tools (Synopsys DC, Cadence Genus, Xilinx Vivado, QuestaSim).
- Proven ability to achieve high-performance and low-power targets.
Good to Have
- Experience with Matlab / NumPy / C / C++ for DSP modeling.
- Exposure to LPDDR, Ethernet, MIPI, or SerDes interfaces.
- Experience in FPGA prototyping or emulation (Palladium, Veloce, Zebu).
- Knowledge of functional safety (ISO and post-silicon bring-up.
Education
- B.E / B.Tech / M.Tech in Electronics or related discipline.
-
ASIC SOC RTL Design Architect
2 weeks ago
Bengaluru, Karnataka, India, Karnataka Eximietas Design Full timeHi All,Eximietas Design Hiring Senior RTL Design (Micro-architecture) Architects / Sr. Manager.Experience: 10+ Years.Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.Anyone with a Valid H1B or Already in US.❖ Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics.❖ Engineering 10+ years of ASIC SOC...
-
ASIC SOC RTL Design Lead
2 weeks ago
Bengaluru, Karnataka, India, Karnataka Eximietas Design Full timeHi All,Eximietas: Eximietas Design is a leading technology consulting and solutions development firm specializing in the VLSI, Cloud Computing, Cyber Security, and AI/ML domains.We are Hiring: ASIC SOC RTL Design Leads/Architect.Experience: 10+ Years.Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.Anyone with a Valid H1B or Already...
-
Senior ASIC RTL Design Engineer
1 week ago
Bengaluru, Karnataka, India Proxelera Full time ₹ 15,00,000 - ₹ 25,00,000 per yearSummary:Own end-to-end RTL design for complex SoC or large subsystem blocks, from micro-architecture through tapeout and silicon bring-up.Responsibilities:Define micro-architecture from specs; write high-quality synthesizable SystemVerilog/Verilog RTL for SoC-level or large subsystems.Own design bring-up, block/subsystem integration, and close on timing,...
-
Lead FPGA Design Engineer
6 days ago
Bengaluru, Karnataka, India Arting Digital Full time ₹ 20,00,000 - ₹ 25,00,000 per yearDescription : - Position : Lead FPGA Design Engineer - Experience : 8yr - Location : Bangalore - Skill Set : FPGA Design, RTL design, digital design,FPGA development, skilled in SystemVerilog/Verilog, AXI4 protocols,and Xilinx Vivado, with strong expertise in DSP and OFDM-based baseband processing. - Working Days : 5Key Responsibilities : ...
-
Lead FPGA Design Engineer
1 week ago
Bengaluru, Karnataka, India Arting Digital Private Limited Full time ₹ 20,00,000 - ₹ 25,00,000 per yearPosition - Lead FPGA Design EngineerExperience - 8yrLocation- BangaloreSkill Set - FPGA Design, RTL design, digital design,FPGA development, skilled in SystemVerilog/Verilog, AXI4 protocols,and Xilinx Vivado, with strong expertise in DSP and OFDM-based baseband processing.Working Days -5Working Timings - 9 to 6 PMKey Responsibilities:Lead RTL architecture...
-
Lead FPGA Design Engineer
6 days ago
Bengaluru, Karnataka, India Arting Digital Full time ₹ 20,00,000 - ₹ 25,00,000 per yearDescriptionPosition : Lead FPGA Design EngineerExperience : 8yrLocation : BangaloreSkill Set : FPGA Design, RTL design, digital design,FPGA development, skilled in SystemVerilog/Verilog, AXI4 protocols,and Xilinx Vivado, with strong expertise in DSP and OFDM-based baseband processing.Working Days : 5Key ResponsibilitiesLead RTL architecture definition,...
-
Senior/Principal ASIC RTL Design Engineer
1 week ago
Bengaluru, Karnataka, India Proxelera Full time ₹ 20,00,000 - ₹ 25,00,000 per yearJob InformationJob Opening IDZR_174_JOBIndustrySemiconductorDate Opened09/10/2025Job TypeFull timeWork Experience8+ YearsCityBangaloreState/ProvinceKarnatakaCountryIndiaZip/Postal Code560078Job DescriptionSummary:Own end-to-end RTL design for complex SoC or large subsystem blocks, from micro-architecture through tapeout and silicon...
-
FPGA SW Validation Engineer R01248
5 days ago
Bengaluru, Karnataka, India Altera Full time ₹ 15,00,000 - ₹ 25,00,000 per yearJob Title:FPGA SW Validation EngineerCompany: AlteraSemiconductor India Pvt LtdLocation :Bengaluru, India EcoSpace, Bellandur ORR)Job ID - R01248Link - Job DescriptionResearches, designs, develops, and optimizes software tools that enable the use of Field Programmable Gate Arrays (FPGA).Develops and optimizes compilers, Partial Reconfiguration (PR) flows,...
-
Bengaluru, Karnataka, India Proxelera Full time ₹ 6,00,000 - ₹ 18,00,000 per yearAbout Proxelera:Proxelera is apremier Outsourced Product Development (OPD) partner, specializing inSemiconductors, Systems, and Bespoke Hardwaresolutions. We combineprocess excellencewithdeep technical expertiseto deliverinnovative and transformative engineering outcomesfor global clients.Proxelera's mission is to empower clients toaccelerate product...
-
Asic Rtl Design Engineer
2 weeks ago
Bengaluru, Karnataka, India Proxelera Full time ₹ 20,00,000 - ₹ 25,00,000 per yearSummary:We are looking for an experienced Senior/Principal ASIC RTL Design Engineer with 10+ years of hands-on RTL design expertise to join our team in Bangalore. The ideal candidate will own end-to-end RTL design for complex SoCs or large subsystems, from micro-architecture through tapeout and silicon bring-up.Job Description:Own RTL design of SoC-level or...
