ASIC RTL Design Engineer

4 days ago


Bengaluru, Karnataka, India Proxelera Full time ₹ 12,00,000 - ₹ 36,00,000 per year

Job Description:

  • Own RTL design of SoC-level or large subsystems from specification to silicon bring-up.
  • Define and implement micro-architecture; write high-quality, synthesizable RTL in SystemVerilog/Verilog.
  • Work closely with physical design teams for synthesis, timing closure, power, area optimization, DFT hooks, and ECOs.
  • Drive block/subsystem integration and ensure seamless bring-up.
  • Collaborate with verification teams to define test plans, assertions (SVA), and coverage goals.
  • Support silicon validation, post-silicon debug, and drive closure of design bugs.
  • Apply low-power design techniques (UPF/retention/isolation) and clock/reset design best practices.
  • Work on standard bus protocols like AXI/ACE/AHB/APB for interconnects, memory subsystems, and I/O integration.
  • Deliver production ASIC tapeouts, owning critical blocks such as interconnects, coherency, memory subsystem, high-speed I/O, security, or power-management islands.
  • Enhance design productivity using Tcl/Python scripting in service of RTL development.

Required Skills:

  • 8+ years of ASIC RTL design
  • Proven track record of multiple production ASIC tapeouts.
  • Expertise in SystemVerilog/Verilog, micro-architecture, clock/reset design, UPF, and low-power techniques.
  • Strong knowledge of AMBA bus protocols AXI/ACE/AHB/APB.
  • Hands-on experience with silicon bring-up and post-silicon debug.


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