Senior/Principal/Lead - ASIC RTL Design Engineer (SOC/Subsystems)

1 day ago

Bengaluru, Karnataka, India Proxelera Full time ₹ 6,00,000 - ₹ 18,00,000 per year

About Proxelera:

Proxelera is a
premier Outsourced Product Development (OPD) partner
, specializing in
Semiconductors, Systems, and Bespoke Hardware
solutions. We combine
process excellence
with
deep technical expertise
to deliver
innovative and transformative engineering outcomes
for global clients.

Proxelera's mission is to empower clients to
accelerate product development
,
optimize performance
, and
scale engineering capabilities
with confidence.

Position:

Senior/Principal/Lead - ASIC RTL Design Engineer

City:
Bangalore

Country:
India

Province:
Karnataka

Job Description
Summary:

Own end-to-end RTL design for complex SoC or large subsystem blocks — from micro-architecture through tapeout and silicon bring-up.

Responsibilities:

  • Define
    micro-architecture
    from specifications; write high-quality, synthesizable
    SystemVerilog/Verilog RTL
    for SoC-level or large subsystems.
  • Own
    design bring-up
    , block/subsystem integration, and close on
    timing, power, and area
    with synthesis and PnR teams.
  • Drive
    design reviews
    , resolve bugs, and support
    silicon validation
    and
    post-silicon debug
    .
  • Collaborate with DV to define
    test plans
    , assertions, and coverage goals; support
    emulation/FPGA
    only as a secondary validation aid (not counted toward the 8 years).

Must-Have Qualifications:

  • 8+ years
    of hands-on ASIC RTL development experience (
    FPGA work does not count toward the 8 years
    ).
  • Multiple production
    ASIC tapeouts
    , owning significant SoC or subsystem functionality (e.g., interconnects, coherency, memory subsystem, high-speed I/O, security, or power-management islands).
  • Strong
    SystemVerilog/Verilog RTL
    and
    micro-architecture
    skills, including clock/reset design, low-power techniques (UPF/retention/isolation), and AMBA/standard bus protocols (AXI/ACE/AHB/APB).
  • Proven collaboration with
    physical design
    teams on synthesis constraints, timing closure, DFT hooks, and ECOs.
  • Demonstrated
    silicon bring-up
    experience for owned blocks/subsystems.

Nice to Have:

  • Exposure to
    coherency protocols
    , cache/memory controllers, DDR/PCIe subsystems, and security/crypto blocks.
  • Experience with
    SVA
    for design-level assertions, performance modeling, or power/performance analysis.
  • Scripting for design productivity (
    Tcl/Python
    ) used to support hands-on RTL work.

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