RTL / Soc Design & Integration Lead

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MTS SILICON DESIGN ENGINEER

The Role
The focus of this role in the AECG ASIC organization is to provide hands-on technical leadership in developing microarchitecture, implementing the design in RTL, RTL Integration etc. ensuring quality (design checks and verification reviews) and PD support for next generation ASICs

The Person
You have a passion for modern, complex SoC architecture with various IO peripherals and heterogeneous processor systems and digital design & verification in general. You are a team player who has excellent communication skills and experience collaborating in a corporate environment with other architects & engineers located in different sites/time-zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Key Responsibilities

• Define and specify micro-architecture of ASIC building blocks and necessary infrastructure based on architecture, PPA, DFT, Functional Safety requirements
• RTL design and debug of complex blocks in Verilog / System Verilog
• Analyze design metrics and make implementation choices to optimize PPA
• RTL Integration
• Work with implementation, verification and physical design teams to achieve high quality design and successful tape out
• Address customer problems through innovative enhancements to product architecture/ micro-architecture
• Collaborate with cross-functional teams to solve novel problems across multiple functional areas in development of clocking features and/or algorithms
• Lead internal and external teams for RTL design

Preferred Experience

• 8+years of experience in an ASIC RTL Design execution role leading to an understanding of end-end development.
• Strong foundation in SoC architecture and processor systems with proven years of experience
• Good analytical problem solving, and attention to details
• Excellent written and verbal communication skills
• Knowledge of CPU, AXI Interconnect, and I/O peripherals
• Knowledge of SOC development flow and accelerator IP
• ASIC design flow and direct experience with ASIC RTL design and Integration.
• Digital design and experience with RTL design in Verilog/System Verilog
• Circuit timing/STA, and practical experience with Prime Time or equivalent tools
• Low power digital design and analysis
• Modern SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation
• TCL, Perl, Python scripting
• Version control systems such as Perforce, ICManage or Git
• Strong verbal and written communication skills
• Ability to organize and present complex technical information
• Fluent in working with Linux environment

Academic Credentials

• BE, B.Tech, BS, ME, MTech, or MS degree in in Electronics, Electrical or Computer Engineering.
• Hands-on Experience in design and integration of complex subsystems or SOC level integration, quality cleanup and delivery to DV, physical design teams. Strong understanding of SOC globals like clocking, reset, boot and power management flows, low power design techniques, security
• Strong technical leader who communicates well with great collaboration skills
• Good understanding of other domains like pre-si verification, Synthesis, and physical design

Benefits offered are described:
AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.