Strategic / Leadership Role - Pd

1 week ago

Hyderabad Telangana, India Advanced Micro Devices Full time

**Strategic / Leadership Role - PD**:

- Hyderabad, India
- Engineering
- 64616

**Job Description**:
**WHAT YOU DO AT AMD CHANGES EVERYTHING**
- We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
- AMD together we advance_

**FELLOW**SILICON DESIGN ENGINEER**

**THE ROLE**:

- We are looking for a Fellow-level Engineer to join our team to develop world-class Server products. In this role you will be engaged with Server SOC architects, micro architecture, RTL, CAD/Methodology, and internal stakeholders to define end to end Power Optimization Methodology, PVT Corners, timing methodology that require technically analyzing, defining usage cases, and mapping across a broad spectrum of technologies to ensure a well-defined methodology to achieve PPA uplift across a spectrum of Server products. In this role you will provide a cohesive technical vision of the required PPA improvement methodology.

**THE PERSON**:

- You will possess very strong problem-solving skills and bring broad experience in methodology, with a strong, self-motivated work ethic.

**KEY RESPONSIBILITIES**:

- Define and drive PPA uplift methodologies for Server products
- Develop and deploy end to end power optimization methodology for Physical Design Implementation
- Define PVT corners, device frequency scaling, frequency targets for next generation Servers in leading foundry technology nodes
- Deep knowledge of micro architecture, power optimization methodologies, Synthesis, Place and Route, Top level Clocking structure and Timing closure.
- Hands-on experience in closing very high-frequency designs
- Proven track record of tapeout experience with leading technology nodes like 10nm, 7nm and 5nm
- Experience driving Physical Implementation methodology
- Excellent communication skills and strong collaboration across multiple business units

**PREFERRED EXPERIENCE**:

- 20+ years’ experience in SOC Physical Design Implementation, Methodology, Signoff and TapeOut
- In-depth experience and deep conceptual understanding of domains like Full Chip Floorplanning, CTS, PnR, STA, PV, EMIR, Low power design, Logic synthesis, LEC/Formality, VSI, etc.
- Presentations, Papers and proven innovations, Patents in these domains is a strong plus
- Forward looking and dependable techincal leader who proactively identifies and resolves issues and roadblocks before they become bottlenecks or showstopper.
- Experience working seamlessly across engineering disciplines and geographies to deliver excellent results

**ACADEMIC CREDENTIALS**:

- Bachelors or Masters degree in computer engineering/Electrical Engineering

LI-SK5

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