STA(Static Timing Analysis) Engineer
3 days ago
Experience: 5+yearsLocation: BangaloreJob Description:As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and process corners.Key Responsibilities:- Own full-chip and block-level timing closure across RTL, synthesis, and physical implementation stages.- Develop and validate timing constraints (SDC) for blocks, partitions, and full-chip designs.- Perform timing analysis using industry-standard tools (e.g., PrimeTime, Tempus).- Collaborate with design and architecture teams to define timing requirements and resolve timing violations.- Analyze timing scenarios, margins, and corner cases.- Integrate third-party IPs and derive timing signoff requirements.- Optimize timing paths and reduce signoff corners by merging modes.- Automate STA flows using scripting languages.- Support test mode timing closure (e.g., scan shift, scan capture, BIST).Primary Skills:- Static Timing Analysis (STA): Deep expertise in STA tools like Synopsys PrimeTime, Cadence Tempus.- Timing Constraints Development: Proficient in writing and validating SDC constraints.- Scripting Languages: Strong skills in TCL, Perl, Python for automation.- ASIC/SoC Design Knowledge: Understanding of synthesis, physical design, and backend flows.- Corner and Mode Analysis: Experience with timing corners, process variations, and signal integrity.- Constraint Debugging: Familiarity with tools like Synopsys GCA (Galaxy Constraint Analyzer).Secondary Skills:- Tool Proficiency: Experience with tools like Genus, Timevision, Fishtail, Tweaker.- Low-Power Design: Knowledge of UPF, multi-voltage domains, and power gating.- Custom IP Integration: Handling of PLLs, SerDes, ADC/DAC, GPIO, HSIO.- Communication & Collaboration: Strong interpersonal skills for cross-functional teamwork.- Mentorship: Ability to guide and mentor junior engineers.- Process Node Experience: Familiarity with advanced nodes (3nm, 5nm, 7nm, FinFET).
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STA(Static Timing Analysis) Engineer
3 weeks ago
Bengaluru, Karnataka, India Capgemini Engineering Full timeExperience: 5+yearsLocation: BangaloreJob Description:As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and process...
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STA(Static Timing Analysis) Engineer
5 hours ago
Bengaluru, India Capgemini Engineering Full timeExperience: 5+yearsLocation: BangaloreJob Description:As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and process...
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STA(Static Timing Analysis) Engineer
3 weeks ago
Bengaluru, Karnataka, India Capgemini Engineering Full timeExperience: 5+years Location: Bangalore Job Description: As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and process...
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STA(Static Timing Analysis) Engineer
2 weeks ago
Bengaluru, Karnataka, India Capgemini Engineering Full timeExperience: 5+yearsLocation: BangaloreJob Description:As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and process...
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STA(Static Timing Analysis) Engineer
2 weeks ago
Bengaluru, Karnataka, India Capgemini Engineering Full timeJob DescriptionExperience: 5+yearsLocation: BangaloreJob Description:As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and...
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STA(Static Timing Analysis) Engineer
7 days ago
Bengaluru, India Capgemini Engineering Full timeExperience: 5+yearsLocation: BangaloreJob Description:As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and process...
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STA(Static Timing Analysis) Engineer
7 days ago
Bengaluru, India Capgemini Engineering Full timeExperience: 5+yearsLocation: BangaloreJob Description:As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and process...
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Static Timing Analysis
4 days ago
Bengaluru, India Eduplex services private limited Full timeStatic Timing Analysis (STA) Lead Location: Bangalore, KAExperience: 7–18 YearsBudget: Up to 30 LPA (DoE)Industry: Semiconductors | ASIC | SoC | AI/Networking ChipsJob Type: Full-Time Job Overview We are seeking a highly skilled Static Timing Analysis (STA) Lead to drive timing closure for large-scale, high-performance ASIC/SoC designs. The ideal candidate...
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SOC Static Timing Analysis Engineer
4 days ago
Bengaluru, India Careernet Full timeKey Skills: Static Timing Analysis,PrimeTime Roles and Responsibilities: Conduct block-level and full-chip static timing analysis across all phases of development. Develop timing methodologies and infrastructure from RTL synthesis to timing closure. Collaborate with architects and designers to define block and chip-level timing constraints. Define analysis...
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Bengaluru, India Capgemini Engineering Full timeExperience: 5+years Location: Bangalore Job Description: As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and process...
