SOC Static Timing Analysis Engineer
4 days ago
Key Skills: Static Timing Analysis,PrimeTime
Roles and Responsibilities:
- Conduct block-level and full-chip static timing analysis across all phases of development.
- Develop timing methodologies and infrastructure from RTL synthesis to timing closure.
- Collaborate with architects and designers to define block and chip-level timing constraints.
- Define analysis scenarios and margin strategies with system and technology teams.
- Establish comprehensive signoff methodology for robust silicon delivery.
- Partner with physical design teams for timing closure and design sign-off.
- Create ASIC timing constraints and drive closure using industry-standard tools.
- Address deep-submicron STA challenges including crosstalk, IR drop, noise, POCV, etc.
- Utilize scripting languages like csh/bash, TCL, and Python for automation.
- Exhibit strong problem-solving, communication, and organizational skills in a fast-paced environment.
Skills Required:
Must-Have:
- Strong expertise in Static Timing Analysis (STA)
- Hands-on experience in block-level and full-chip timing analysis
- Deep understanding of timing closure methodologies
- Proficiency in scripting languages: TCL, Python, csh/bash
- Knowledge of ASIC timing constraints and RTL-to-GDS flow
- Familiarity with deep-submicron STA issues: crosstalk delay, noise glitch, POCV, IR-STA
Nice-to-Have:
- Experience with PrimeTime or Tempus timing tools
- Exposure to timing signoff methodologies and EDA tools
- Strong collaboration and communication skills
- Ability to work under aggressive schedules with cross-functional teams
Education: PhD, Master's Degree or Bachelor's Degree in Electrical Engineering (EE), Electrical Engineering and Computer Science (EECS), or Computer Science (CS).
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