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Staff Architect

2 months ago

Noida, Uttar Pradesh, India Renesas Electronics Full time
Description

We are seeking a highly skilled Staff Engineer to join our Verification R&D team in Renesas Electronics. As a Staff Engineer, you will be responsible for driving technical execution and best-in-class methodologies used in the design of advanced microcontrollers and microprocessors.



Key Responsibilities:

  • Contribute to the development of high-level specifications that are implementable and robust.
  • Interface with verification/validation teams to ensure design quality and robustness.
  • Practice strong collaboration with other R&D teams such as Verification, digital IP, Design Enablement, Emulation, and Validation to achieve project milestones.
  • Promote continuous improvement to design techniques to ensure 'Zero Defect' chips.
  • Collaborate with SME's and key leaders in architecture, systems, emulation, SoC design, software, physical design, and IP teams developing key technical networks to influence overall design improvements and verification methodologies.
  • Contribute driving best-in-class verification methodologies collaborating with global internal and external SME's and developing adoption and compliance processes.
  • Participate in customer engagements assessing quality and risks.


Qualifications:

  • 5+ years of experience on IP/Sub-System Verification.
  • Experience in testbench design and development using UVM methodology for IP/Subsystem and SOC.
  • Experience in Microcontroller and Microprocessor architecture, Interconnect, Cache Coherency.
  • Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers.
  • Good knowledge of Verilog, System Verilog, C/C++, Shell.
  • Good knowledge in scripting like Perl, TCL or Python is a plus.
  • Proficiency in Metric Driven Verification concepts, functional and code coverage.
  • Expertise in directed and constrained random methodologies.
  • Good knowledge of formal verification methodologies and assertions.
  • Experience with debugging of designs pre- and post-silicon, in simulation and on the bench.
  • Excellent written and verbal communication skill.
  • Experience with System Verilog and front-end tooling (simulation, waveform viewers, lint, CDC, RDC, etc.) is required, as well as highly efficient FE methodologies.
  • Experience working with complex, multi-core SoC's with extensive interconnects and a large range of peripherals is preferred.
  • Domain knowledge of clocking, system modes, power management, debug, security and other architectures is preferred.
  • Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems.