Subsystem Timing Expert

3 days ago

Bengaluru, Karnataka, India beBeeStaticTimingAnalysis Full time ₹ 2,40,52,832 - ₹ 2,98,64,378

Job Summary

Oversee static timing analysis and place and route for complex subsystems, ensuring robust timing closure, power efficiency, performance optimization, and area reduction.

Key Responsibilities

Develop methodologies for static timing analysis and place and route tailored to large, multi-interface, or mixed-signal subsystems.

Implement automation and validation of timing and physical design data across subsystem boundaries.

Mentor junior engineers in technical growth and knowledge sharing within subsystem teams.

Collaborate with cross-functional teams to resolve design, timing, and physical implementation challenges in complex subsystem integration.

Present technical solutions and lead discussions on subsystem-level trade-offs and integration.

Requirements

Minimum 10 years of experience in static timing analysis and place and route for complex subsystems in ASIC/SoC design, including advanced technology nodes (7nm or below).

Expertise in static timing analysis tools (e.g., Synopsys PrimeTime, Cadence Tempus) and place and route tools (e.g., Synopsys ICC2, Cadence Innovus) applied to large, multi-block or hierarchical subsystems.

Proficiency in scripting languages (Tcl, Perl, Python) for automating static timing analysis and place and route flows across multiple subsystem blocks.

Familiarity with SoC design flows, having collaborated across frontend, physical design, and verification teams to integrate complex subsystems.

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