Memory Subsystem Verification Expert

2 days ago

Bengaluru, Karnataka, India beBeeVerification Full time ₹ 24,00,000 - ₹ 30,00,000

Are you passionate about the latest advancements in AI, ML, and datacenter technologies?

We have an exciting opportunity for a skilled Memory Subsystem Design Verification Engineer to join our team

In this role, you will collaborate with architects and RTL designers to verify DDR and HBM memory subsystem feature sets.

You will work closely with third-party IP vendors to validate IP integration and ensure custom feature correctness.

Key responsibilities include developing verification test plans and testbenches based on design specifications.

You will also integrate and bring up Verification IPs (VIPs) such as DDR_PHY and memory models into UVM environments.

An added bonus is that you will develop drivers, checkers, and scoreboards using SystemVerilog/UVM.

Finally, you will be responsible for debugging, maintaining regression, and driving functional and code coverage closure.

Requirements
  • Hands-on experience verifying digital logic of DDR/HBM memory subsystems.
  • Solid understanding of JEDEC specifications for LPDDRx/DDRx/HBMx.
  • Familiarity with DDR PHY interface (DFI) protocols and specifications.
  • Knowledge of RAS (Reliability, Availability, and Serviceability) features in memory subsystems.
Benefits

This is an amazing opportunity to grow your career and expand your professional network.

As a member of our team, you will receive continuous learning opportunities and career advancement paths.

About Us

We are committed to delivering cutting-edge technology solutions that meet the needs of our clients.

We believe in investing in our engineers' growth and development, providing them with the tools and resources they need to succeed.

Your success is our top priority

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