Memory Subsystem Design Verification

3 weeks ago

Bengaluru, Karnataka, India Eteros Technologies Full time

Company: Eteros Technologies India Private Limited

Eteros Technologies, Inc. is a Semiconductor Engineering services startup, head quartered in the heart of the Silicon Valley, San Jose, CA, USA. Eteros Technologies India Pvt Ltd is a wholly owned subsidiary offices in Bangalore, Noida, Hyderabad and Ahmedabad


• Our world-wide customers are amongst The Who's who in the semiconductor industry. Eteros works not only with some of the top 20 semiconductor startups in the world but boasts of customers who are among the most respected publicly traded semiconductor companies.


• Eteros engineers work on cutting edge technology nodes while working on the state-of-the art designs in the AI/ML, Datacenter, Automotive and 5G domains. Eteros engineers work with some of the brightest, innovative and successful engineers and leaders around the world. A one-of-a-kind opportunity where young Eteros engineers showcase their ability and experience world-wide from day 1 while learning from some of the world's most well-respected companies.


• We are not your traditional design services company offering staff augmentation. Eteros engineers are treated as an integral part of the customer team and routinely are responsible for turnkey, end-to-end ownership and delivery, whether it is Implementation, Digital and Mixed Signal Verification, DFT or Analog Design and Layout. Eteros and our engineers work closely with our customers to define and set methodologies and design flows.


• Eteros invests in our engineers. Our engineers are continuously learning, on and off the job. They are able to grow the breadth and depth of knowledge. We believe in preparing our employees for the fast-track in career development as well as longevity

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Responsibilities :

  • Collaborate with architects and RTL designers to verify DDR and HBM memory subsystem feature sets.
  • Work closely with third-party IP vendors to validate IP integration and ensure custom feature correctness.
  • Develop verification test plans and testbenches based on design specifications.
  • Integrate and bring up Verification IPs (VIPs) such as DDR_PHY and memory models into UVM environments.
  • Develop drivers, checkers, and scoreboards using SystemVerilog/UVM.
  • Debugging, maintain regression and drive functional and code coverage closure.

Requirements :

  • Proven hands-on experience verifying the digital logic of DDR/HBM memory subsystems.
  • Solid understanding of JEDEC specifications for LPDDRx/DDRx/HBMx
  • Knowledge of DDR PHY interface (DFI) protocols and specifications.
  • Familiarity with RAS (Reliability, Availability, and Serviceability) features in memory subsystems:

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