Design Verification
3 days ago
- 12-18 Yrs in DV full-chip Exp.
- Experience in SV/UVM testbench verification
- Experience in ARM Coresight Debug subsystem
- CSI/ DSI protocol expertise
- Memory controller or cache expertise
- Hands-on RAL model development (UVM)
Required Candidate profile
• EXP in verifying successful IPs, Subsystems & or SoCs.
• PC System Architecture: PCI Express, USB, Ethernet, HyperTransport, DDR.
• Standard bus/interface protocols (i.e. AXI, AHB, AMBA, OCP, PIPE).
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Design Verification Engineer
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Design Verification
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Design Verification
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