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Senior Memory Verification Specialist
2 weeks ago
We are seeking a skilled Memory Subsystem Verification Engineer to join our team.
The ideal candidate will have hands-on experience verifying digital logic for memory subsystems, including DDR and HBM. They should also possess a solid understanding of JEDEC specifications, as well as knowledge of DDR PHY interface protocols and RAS features in memory subsystems.
Key Responsibilities:- Collaborate with architects and designers to verify memory subsystem feature sets.
- Work closely with third-party IP vendors to validate IP integration and ensure custom feature correctness.
- Develop verification test plans and testbenches based on design specifications.
- Integrate and bring up Verification IPs (VIPs) into UVM environments.
- Develop drivers, checkers, and scoreboards using SystemVerilog/UVM.
- Debugging, maintain regression and drive functional and code coverage closure.
- Proven experience in verifying digital logic for memory subsystems.
- Solid understanding of JEDEC specifications.
- Knowledge of DDR PHY interface protocols.
- Familiarity with RAS features in memory subsystems.
