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1 week ago
We are seeking an experienced Memory Subsystem Design Verification Engineer to join our team.
Job DescriptionThis is a key role in the verification of memory subsystems, requiring strong expertise in digital logic and JEDEC specifications.
The ideal candidate will have a proven track record of verifying DDR and HBM memory subsystem feature sets, as well as experience with third-party IP vendors and UVM environments.
Responsibilities include developing verification test plans and testbenches, integrating VIPs into UVM environments, and debugging issues with drivers, checkers, and scoreboards.
Requirements- Proven experience verifying digital logic of DDR/HBM memory subsystems.
- Solid understanding of JEDEC specifications for LPDDRx/DDRx/HBMx.
- Familiarity with RAS features in memory subsystems.
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