Embedded Memory Designer

19 hours ago

Bengaluru, Karnataka, India beBeeMemory Full time US$ 1,50,000 - US$ 2,00,000
Senior Memory Design Engineer

You will thrive in a collaborative work environment with a proven track record of designing and developing cutting-edge embedded memories such as SP SRAM, DP SRAM, Register File, and ROM. Your expertise in ultra-high-speed, ultra-low-power, or high-density design portfolios sets you apart.

  • Develop CMOS embedded memories, focusing on ultra-high-speed, ultra-low-power, or high-density design portfolios.
  • Perform schematic entry, circuit simulation, layout planning, layout supervision, design verification, and validation.
  • Interface with CAD and Frontend engineers for memory compiler automation, EDA model generation, and full verification flow.
  • Drive physical layout design and verification, and provide support and/or perform other duties as assigned.
Key Responsibilities:

  1. Contribute to the development of innovative CMOS embedded memory technologies.
  2. Enhance the efficiency and performance of memory design processes through automation and verification.
  3. Support the integration of advanced memory technologies into high-performance silicon chips.
  4. Collaborate with cross-functional teams to deliver state-of-the-art memory solutions.
Requirements:

  • Bachelor's or Master's degree in Electrical Engineering, Telecommunication, or related fields.
  • Minimum 5+ years of experience in memory design, circuit simulation, memory layout designs, layout parasitic extraction, and knowledge of layout verification tools and debugging techniques.
  • Programming capability in C-Shell, Perl; knowledge of C++ or JavaScript is a plus.
  • Excellent analytical and problem-solving skills with attention to detail.
What We Offer:

  • Comprehensive range of health, wellness, and financial benefits to cater to your needs.
  • Total rewards include both monetary and non-monetary offerings.
About Us:

Our team collaborates closely with CAD and Frontend engineers to drive automation and verification processes, ensuring the highest performance and efficiency in memory design.

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