
Verification Engineer
2 days ago
Job Description
We are seeking a skilled verification engineer to develop and implement comprehensive verification plans for subsystem components and IPs.
Key Responsibilities:
- Develop test plans, build testbenches, and create verification flows using SystemVerilog and UVM methodology.
- Drive functional verification of RTL designs at the subsystem level or SoC level, including simulation, debugging, and coverage closure.
- Collaborate with design engineers to understand detailed design specifications and target corner cases.
- Generate and analyze verification metrics to track progress and ensure timely coverage closure.
- Participate in design and verification reviews, providing technical expertise.
Requirements:
- Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or related fields.
- Proficiency in verification languages and methodologies.
- Excellent problem-solving skills and attention to detail.
- Strong oral and written communication skills.
- 4-15 years of experience in design verification, with a focus on Subsystem/SoC verification.
What We Offer:
- A challenging role in a dynamic environment.
- Opportunities for professional growth and development.
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