
Verification Engineer
2 days ago
Design Verification Specialist
We are seeking an experienced Design Verification Engineer to join our team.
- Define and implement IP/Sub-System/SoC level verification plans, test benches, and functional tests.
- Develop verification environments and architect design verification infrastructure.
- Debug, root-cause, and resolve functional failures in the design.
Requirements:
- Bachelor's or Master's degree in Computer Science, Electronics Engineering, or equivalent practical experience.
- 5+ years of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification.
- Experience in development of UVM-based verification environments from scratch.
- Experience with verification of ARM/RISC-V based CPU sub-systems or SoCs, as well as IP or integration verification.
- Proficiency in E-tools and scripting languages like Python, TCL, Perl, Shell used to build tools and flows for verification environments.
The successful candidate will possess excellent problem-solving skills, be able to work independently, and have strong communication skills. We offer a challenging opportunity for a skilled Design Verification Specialist.
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