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Senior ASIC Design Expert

3 weeks ago

Cochin, Kerala, India beBeeDesign Full time ₹ 2,00,00,000 - ₹ 2,50,00,000
Job Opportunity

We are seeking a highly skilled Physical Design Engineer to join our team.

The ideal candidate will have a strong background in ASIC physical design and experience with EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, internal tools & flow, etc.

In this role, you will be responsible for all aspects of Physical Design for Fullchip/Blocks covering Floorplanning, Placement, Budgeting, Clock Tree planning & analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, Low Power solution development & implementation.

  • You will work closely with the methodology team to solve the implementation challenges & provide inputs to improve the Physical design flow.
  • Proficient in Unix/TCL/Perl programming languages.
  • Good communication and presentation skills. Requires good interpersonal skills and problem-solving ability.

Key Responsibilities:

  • Physical Design for Fullchip/Blocks.
  • Floorplanning, Placement, Budgeting, Clock Tree planning & analysis.
  • Scan re-ordering, Clock tree synthesis, Placement optimizations.
  • Routing, Timing and SI analysis/closure.
  • ECO tasks (both timing and functional).
  • EM/IR, DRC, LVS, ERC analysis & fixes.
  • Low Power solution development & implementation.

Required Skills and Qualifications:

  • 4+ years experience in ASIC physical design.
  • Experience with block implementation, extraction, timing and or full-chip designs.
  • Strong communication skills.
  • Strong hands-on TCL/Perl development skills.

Benefits:

  • Excellent compensation package.
  • Opportunities for professional growth and development.
  • A collaborative and dynamic work environment.

Others:

  • Must have prior experience with Synopsys/Cadence/Mentor place and route tools.
  • Must have completed design in 16nm and or 7nm.
  • Track record of taping out complex chips on advanced process nodes.