Senior Design Assurance Specialist

2 weeks ago

Cochin, Kerala, India beBeeVerification Full time ₹ 18,16,075 - ₹ 24,31,425
Design Verification Engineer Position

This is an exciting opportunity to join our organization as a skilled Design Verification Engineer. As a key member of our team, you will play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs.

The successful candidate will have a strong foundation in verification methodologies and be able to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits.

Key Responsibilities:

  • Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification)
  • Create high-quality verification environments (testbenches) to achieve exceptional code coverage
  • Utilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionality
  • Debug and analyze verification failures with a keen eye to identify and resolve the root cause of design issues
  • Collaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherence
  • Lead and mentor junior DV engineers within the team, fostering a collaborative and knowledge-sharing environment
  • Participate in code reviews and champion best practices for verification code quality
  • Stay current with the latest advancements in verification tools and methodologies

Qualifications and Skills:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus)
  • 7-10 years of solid experience in Design Verification for ASICs or SoCs
  • In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines)
  • Proven ability to develop, debug, and optimize complex verification environments
  • Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal)
  • Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl)
  • Experience with formal verification tools and techniques is a plus
  • Excellent analytical and problem-solving skills with a meticulous attention to detail
  • Strong communication, collaboration, and leadership skills to effectively contribute and guide the team

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